6613 	u32 dcore_offset = dcore_id * DCORE_OFFSET;  in gaudi2_mmu_dcore_prepare()  local
6620 		WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6621 		WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6622 		WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6623 		WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6627 		WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6628 		WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6629 		WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6630 		WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6634 	WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid);  in gaudi2_mmu_dcore_prepare()
6642 		WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID + dcore_offset, reg_val);  in gaudi2_mmu_dcore_prepare()
6643 		WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6646 	WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6647 	WREG32(mmDCORE0_MME_CTRL_LO_MME_AXUSER_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6652 				dcore_offset + ports_offset, 0);  in gaudi2_mmu_dcore_prepare()
6654 				dcore_offset + ports_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6660 				dcore_offset + ports_offset, 0);  in gaudi2_mmu_dcore_prepare()
6662 				dcore_offset + ports_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()
6665 	WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);  in gaudi2_mmu_dcore_prepare()
6666 	WREG32(mmDCORE0_MME_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);  in gaudi2_mmu_dcore_prepare()