Lines Matching defs:asic_fixed_properties
684 struct asic_fixed_properties { struct
685 struct hw_queue_properties *hw_queues_props;
686 struct cpucp_info cpucp_info;
687 char uboot_ver[VERSION_MAX_LEN];
688 char preboot_ver[VERSION_MAX_LEN];
689 struct hl_mmu_properties dmmu;
690 struct hl_mmu_properties pmmu;
691 struct hl_mmu_properties pmmu_huge;
692 struct hl_hints_range hints_dram_reserved_va_range;
693 struct hl_hints_range hints_host_reserved_va_range;
694 struct hl_hints_range hints_host_hpage_reserved_va_range;
695 u64 sram_base_address;
696 u64 sram_end_address;
697 u64 sram_user_base_address;
698 u64 dram_base_address;
699 u64 dram_end_address;
700 u64 dram_user_base_address;
701 u64 dram_size;
702 u64 dram_pci_bar_size;
703 u64 max_power_default;
704 u64 dc_power_default;
705 u64 dram_size_for_default_page_mapping;
706 u64 pcie_dbi_base_address;
707 u64 pcie_aux_dbi_reg_addr;
708 u64 mmu_pgt_addr;
709 u64 mmu_dram_default_page_addr;
710 u64 tpc_enabled_mask;
711 u64 tpc_binning_mask;
712 u64 dram_enabled_mask;
713 u64 dram_binning_mask;
714 u64 dram_hints_align_mask;
715 u64 cfg_base_address;
716 u64 mmu_cache_mng_addr;
717 u64 mmu_cache_mng_size;
718 u64 device_dma_offset_for_host_access;
719 u64 host_base_address;
720 u64 host_end_address;
721 u64 max_freq_value;
722 u32 clk_pll_index;
723 u32 mmu_pgt_size;
724 u32 mmu_pte_size;
725 u32 mmu_hop_table_size;
726 u32 mmu_hop0_tables_total_size;
727 u32 dram_page_size;
728 u32 cfg_size;
729 u32 sram_size;
730 u32 max_asid;
731 u32 num_of_events;
732 u32 psoc_pci_pll_nr;
733 u32 psoc_pci_pll_nf;
734 u32 psoc_pci_pll_od;
735 u32 psoc_pci_pll_div_factor;
736 u32 psoc_timestamp_frequency;
737 u32 high_pll;
738 u32 cb_pool_cb_cnt;
739 u32 cb_pool_cb_size;
740 u32 decoder_enabled_mask;
741 u32 decoder_binning_mask;
742 u32 edma_enabled_mask;
743 u32 edma_binning_mask;
744 u32 max_pending_cs;
745 u32 max_queues;
746 u32 fw_preboot_cpu_boot_dev_sts0;
747 u32 fw_preboot_cpu_boot_dev_sts1;
748 u32 fw_bootfit_cpu_boot_dev_sts0;
749 u32 fw_bootfit_cpu_boot_dev_sts1;
750 u32 fw_app_cpu_boot_dev_sts0;
751 u32 fw_app_cpu_boot_dev_sts1;
752 u32 max_dec;
753 u32 hmmu_hif_enabled_mask;
754 u32 faulty_dram_cluster_map;
755 u32 xbar_edge_enabled_mask;
756 u32 device_mem_alloc_default_page_size;
757 u32 num_engine_cores;
758 u16 collective_first_sob;
759 u16 collective_first_mon;
760 u16 sync_stream_first_sob;
761 u16 sync_stream_first_mon;
762 u16 first_available_user_sob[HL_MAX_DCORES];
763 u16 first_available_user_mon[HL_MAX_DCORES];
764 u16 first_available_user_interrupt;
765 u16 first_available_cq[HL_MAX_DCORES];
766 u16 user_interrupt_count;
767 u16 user_dec_intr_count;
768 u16 cache_line_size;
769 u16 server_type;
770 u8 completion_queues_count;
771 u8 completion_mode;
772 u8 mme_master_slave_mode;
773 u8 fw_security_enabled;
774 u8 fw_cpu_boot_dev_sts0_valid;
775 u8 fw_cpu_boot_dev_sts1_valid;
776 u8 dram_supports_virtual_memory;
777 u8 hard_reset_done_by_fw;
778 u8 num_functional_hbms;
779 u8 hints_range_reservation;
780 u8 iatu_done_by_fw;
781 u8 dynamic_fw_load;
782 u8 gic_interrupts_enable;
783 u8 use_get_power_for_reset_history;
784 u8 supports_compute_reset;
785 u8 allow_inference_soft_reset;
786 u8 configurable_stop_on_err;
787 u8 set_max_power_on_device_init;
788 u8 supports_user_set_page_size;
789 u8 dma_mask;
790 u8 supports_advanced_cpucp_rc;