Lines Matching refs:pcr
18 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr) in rts5261_get_ic_version() argument
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5261_get_ic_version()
26 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5261_fill_driving() argument
44 drive_sel = pcr->sd30_drive_sel_3v3; in rts5261_fill_driving()
47 drive_sel = pcr->sd30_drive_sel_1v8; in rts5261_fill_driving()
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, in rts5261_fill_driving()
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, in rts5261_fill_driving()
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, in rts5261_fill_driving()
60 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) in rts5261_force_power_down() argument
63 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rts5261_force_power_down()
64 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rts5261_force_power_down()
65 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, in rts5261_force_power_down()
69 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5261_force_power_down()
73 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, in rts5261_force_power_down()
75 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5261_force_power_down()
76 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_force_power_down()
80 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_force_power_down()
83 rtsx_pci_write_register(pcr, RTS5261_FW_CTL, in rts5261_force_power_down()
85 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, in rts5261_force_power_down()
90 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL, in rts5261_force_power_down()
94 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr) in rts5261_enable_auto_blink() argument
96 return rtsx_pci_write_register(pcr, OLT_LED_CTL, in rts5261_enable_auto_blink()
100 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr) in rts5261_disable_auto_blink() argument
102 return rtsx_pci_write_register(pcr, OLT_LED_CTL, in rts5261_disable_auto_blink()
106 static int rts5261_turn_on_led(struct rtsx_pcr *pcr) in rts5261_turn_on_led() argument
108 return rtsx_pci_write_register(pcr, GPIO_CTL, in rts5261_turn_on_led()
112 static int rts5261_turn_off_led(struct rtsx_pcr *pcr) in rts5261_turn_off_led() argument
114 return rtsx_pci_write_register(pcr, GPIO_CTL, in rts5261_turn_off_led()
144 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) in rts5261_sd_set_sample_push_timing_sd30() argument
146 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK in rts5261_sd_set_sample_push_timing_sd30()
148 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in rts5261_sd_set_sample_push_timing_sd30()
149 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, in rts5261_sd_set_sample_push_timing_sd30()
151 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_sd_set_sample_push_timing_sd30()
156 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card) in rts5261_card_power_on() argument
158 struct rtsx_cr_option *option = &pcr->option; in rts5261_card_power_on()
161 rtsx_pci_enable_ocp(pcr); in rts5261_card_power_on()
163 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, in rts5261_card_power_on()
166 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1, in rts5261_card_power_on()
168 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, in rts5261_card_power_on()
171 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, in rts5261_card_power_on()
176 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); in rts5261_card_power_on()
179 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, in rts5261_card_power_on()
182 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, in rts5261_card_power_on()
184 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); in rts5261_card_power_on()
185 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, in rts5261_card_power_on()
189 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); in rts5261_card_power_on()
190 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, in rts5261_card_power_on()
194 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || in rts5261_card_power_on()
195 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) in rts5261_card_power_on()
196 rts5261_sd_set_sample_push_timing_sd30(pcr); in rts5261_card_power_on()
201 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts5261_switch_output_voltage() argument
206 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL, in rts5261_switch_output_voltage()
211 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); in rts5261_switch_output_voltage()
213 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); in rts5261_switch_output_voltage()
217 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG, in rts5261_switch_output_voltage()
219 rtsx_pci_write_register(pcr, SD_PAD_CTL, in rts5261_switch_output_voltage()
223 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); in rts5261_switch_output_voltage()
225 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); in rts5261_switch_output_voltage()
229 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG, in rts5261_switch_output_voltage()
231 rtsx_pci_write_register(pcr, SD_PAD_CTL, in rts5261_switch_output_voltage()
239 rts5261_fill_driving(pcr, voltage); in rts5261_switch_output_voltage()
244 static void rts5261_stop_cmd(struct rtsx_pcr *pcr) in rts5261_stop_cmd() argument
246 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); in rts5261_stop_cmd()
247 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); in rts5261_stop_cmd()
248 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0, in rts5261_stop_cmd()
251 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); in rts5261_stop_cmd()
254 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr) in rts5261_card_before_power_off() argument
256 rts5261_stop_cmd(pcr); in rts5261_card_before_power_off()
257 rts5261_switch_output_voltage(pcr, OUTPUT_3V3); in rts5261_card_before_power_off()
261 static void rts5261_enable_ocp(struct rtsx_pcr *pcr) in rts5261_enable_ocp() argument
266 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_enable_ocp()
269 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); in rts5261_enable_ocp()
273 static void rts5261_disable_ocp(struct rtsx_pcr *pcr) in rts5261_disable_ocp() argument
278 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rts5261_disable_ocp()
279 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_disable_ocp()
284 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card) in rts5261_card_power_off() argument
288 rts5261_card_before_power_off(pcr); in rts5261_card_power_off()
289 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL, in rts5261_card_power_off()
292 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, in rts5261_card_power_off()
294 if (pcr->option.ocp_en) in rts5261_card_power_off()
295 rtsx_pci_disable_ocp(pcr); in rts5261_card_power_off()
300 static void rts5261_init_ocp(struct rtsx_pcr *pcr) in rts5261_init_ocp() argument
302 struct rtsx_cr_option *option = &pcr->option; in rts5261_init_ocp()
307 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
311 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
314 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
319 val = pcr->hw_param.ocp_glitch; in rts5261_init_ocp()
320 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); in rts5261_init_ocp()
322 rts5261_enable_ocp(pcr); in rts5261_init_ocp()
324 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0, in rts5261_init_ocp()
329 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr) in rts5261_clear_ocpstat() argument
337 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); in rts5261_clear_ocpstat()
340 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rts5261_clear_ocpstat()
344 static void rts5261_process_ocp(struct rtsx_pcr *pcr) in rts5261_process_ocp() argument
346 if (!pcr->option.ocp_en) in rts5261_process_ocp()
349 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); in rts5261_process_ocp()
351 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { in rts5261_process_ocp()
352 rts5261_clear_ocpstat(pcr); in rts5261_process_ocp()
353 rts5261_card_power_off(pcr, RTSX_SD_CARD); in rts5261_process_ocp()
354 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rts5261_process_ocp()
355 pcr->ocp_stat = 0; in rts5261_process_ocp()
360 static void rts5261_init_from_hw(struct rtsx_pcr *pcr) in rts5261_init_from_hw() argument
362 struct pci_dev *pdev = pcr->pci; in rts5261_init_from_hw()
367 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_init_from_hw()
371 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR, in rts5261_init_from_hw()
373 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL, in rts5261_init_from_hw()
379 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp); in rts5261_init_from_hw()
383 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp); in rts5261_init_from_hw()
385 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid); in rts5261_init_from_hw()
388 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2); in rts5261_init_from_hw()
392 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_init_from_hw()
394 pcr_dbg(pcr, "Disable efuse por!\n"); in rts5261_init_from_hw()
415 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2); in rts5261_init_from_hw()
419 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rts5261_init_from_hw()
420 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rts5261_init_from_hw()
425 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rts5261_init_from_hw()
427 pcr->rtd3_en = rts5261_reg_to_rtd3(lval2); in rts5261_init_from_hw()
430 pcr->flags |= PCR_REVERSE_SOCKET; in rts5261_init_from_hw()
433 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1); in rts5261_init_from_hw()
435 pcr->aspm_en = rts5261_reg_to_aspm(lval1); in rts5261_init_from_hw()
436 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1); in rts5261_init_from_hw()
437 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1); in rts5261_init_from_hw()
441 rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF)); in rts5261_init_from_hw()
442 rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF)); in rts5261_init_from_hw()
443 rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF)); in rts5261_init_from_hw()
444 rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF)); in rts5261_init_from_hw()
445 rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF)); in rts5261_init_from_hw()
446 rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF)); in rts5261_init_from_hw()
447 rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF)); in rts5261_init_from_hw()
455 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr) in rts5261_init_from_cfg() argument
457 struct pci_dev *pdev = pcr->pci; in rts5261_init_from_cfg()
460 struct rtsx_cr_option *option = &pcr->option; in rts5261_init_from_cfg()
469 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); in rts5261_init_from_cfg()
471 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN); in rts5261_init_from_cfg()
474 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); in rts5261_init_from_cfg()
476 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN); in rts5261_init_from_cfg()
479 rtsx_set_dev_flag(pcr, PM_L1_1_EN); in rts5261_init_from_cfg()
481 rtsx_clear_dev_flag(pcr, PM_L1_1_EN); in rts5261_init_from_cfg()
484 rtsx_set_dev_flag(pcr, PM_L1_2_EN); in rts5261_init_from_cfg()
486 rtsx_clear_dev_flag(pcr, PM_L1_2_EN); in rts5261_init_from_cfg()
488 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); in rts5261_init_from_cfg()
496 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5261_init_from_cfg()
502 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5261_init_from_cfg()
509 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) in rts5261_extra_init_hw() argument
511 struct rtsx_cr_option *option = &pcr->option; in rts5261_extra_init_hw()
514 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1, in rts5261_extra_init_hw()
517 rts5261_init_from_cfg(pcr); in rts5261_extra_init_hw()
518 rts5261_init_from_hw(pcr); in rts5261_extra_init_hw()
521 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_extra_init_hw()
523 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, in rts5261_extra_init_hw()
525 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); in rts5261_extra_init_hw()
527 if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) { in rts5261_extra_init_hw()
528 val = rtsx_pci_readl(pcr, RTSX_DUM_REG); in rts5261_extra_init_hw()
529 rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1); in rts5261_extra_init_hw()
531 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, in rts5261_extra_init_hw()
535 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4, in rts5261_extra_init_hw()
537 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts5261_extra_init_hw()
540 rtsx_pci_write_register(pcr, PCLK_CTL, in rts5261_extra_init_hw()
543 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts5261_extra_init_hw()
544 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN); in rts5261_extra_init_hw()
547 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); in rts5261_extra_init_hw()
550 rts5261_fill_driving(pcr, OUTPUT_3V3); in rts5261_extra_init_hw()
552 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5261_extra_init_hw()
553 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); in rts5261_extra_init_hw()
555 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00); in rts5261_extra_init_hw()
562 rtsx_pci_write_register(pcr, PETXCFG, in rts5261_extra_init_hw()
565 rtsx_pci_write_register(pcr, PETXCFG, in rts5261_extra_init_hw()
568 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); in rts5261_extra_init_hw()
570 if (pcr->rtd3_en) { in rts5261_extra_init_hw()
571 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01); in rts5261_extra_init_hw()
572 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_extra_init_hw()
576 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5261_extra_init_hw()
577 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL, in rts5261_extra_init_hw()
580 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00); in rts5261_extra_init_hw()
583 rtsx_pci_write_register(pcr, RTS5261_FW_CTL, in rts5261_extra_init_hw()
589 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable) in rts5261_enable_aspm() argument
594 if (pcr->aspm_enabled == enable) in rts5261_enable_aspm()
597 val |= (pcr->aspm_en & 0x02); in rts5261_enable_aspm()
598 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5261_enable_aspm()
599 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5261_enable_aspm()
600 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); in rts5261_enable_aspm()
601 pcr->aspm_enabled = enable; in rts5261_enable_aspm()
604 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable) in rts5261_disable_aspm() argument
609 if (pcr->aspm_enabled == enable) in rts5261_disable_aspm()
612 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5261_disable_aspm()
614 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5261_disable_aspm()
615 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); in rts5261_disable_aspm()
617 pcr->aspm_enabled = enable; in rts5261_disable_aspm()
620 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable) in rts5261_set_aspm() argument
623 rts5261_enable_aspm(pcr, true); in rts5261_set_aspm()
625 rts5261_disable_aspm(pcr, false); in rts5261_set_aspm()
628 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5261_set_l1off_cfg_sub_d0() argument
630 struct rtsx_cr_option *option = &pcr->option; in rts5261_set_l1off_cfg_sub_d0()
634 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5261_set_l1off_cfg_sub_d0()
635 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5261_set_l1off_cfg_sub_d0()
647 rtsx_set_l1off_sub(pcr, val); in rts5261_set_l1off_cfg_sub_d0()
675 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, in rts5261_pci_switch_clock() argument
690 if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) { in rts5261_pci_switch_clock()
700 err = rtsx_pci_write_register(pcr, SD_CFG1, in rts5261_pci_switch_clock()
706 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); in rts5261_pci_switch_clock()
711 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", in rts5261_pci_switch_clock()
712 clk, pcr->cur_clock); in rts5261_pci_switch_clock()
714 if (clk == pcr->cur_clock) in rts5261_pci_switch_clock()
717 if (pcr->ops->conv_clk_and_div_n) in rts5261_pci_switch_clock()
718 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); in rts5261_pci_switch_clock()
730 if (pcr->ops->conv_clk_and_div_n) { in rts5261_pci_switch_clock()
731 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, in rts5261_pci_switch_clock()
733 n = pcr->ops->conv_clk_and_div_n(dbl_clk, in rts5261_pci_switch_clock()
742 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); in rts5261_pci_switch_clock()
768 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); in rts5261_pci_switch_clock()
770 rtsx_pci_init_cmd(pcr); in rts5261_pci_switch_clock()
771 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, in rts5261_pci_switch_clock()
773 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5261_pci_switch_clock()
775 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rts5261_pci_switch_clock()
776 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, in rts5261_pci_switch_clock()
778 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rts5261_pci_switch_clock()
779 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in rts5261_pci_switch_clock()
781 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rts5261_pci_switch_clock()
783 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, in rts5261_pci_switch_clock()
785 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rts5261_pci_switch_clock()
787 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, in rts5261_pci_switch_clock()
791 err = rtsx_pci_send_cmd(pcr, 2000); in rts5261_pci_switch_clock()
797 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rts5261_pci_switch_clock()
801 pcr->cur_clock = clk; in rts5261_pci_switch_clock()
806 void rts5261_init_params(struct rtsx_pcr *pcr) in rts5261_init_params() argument
808 struct rtsx_cr_option *option = &pcr->option; in rts5261_init_params()
809 struct rtsx_hw_param *hw_param = &pcr->hw_param; in rts5261_init_params()
812 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5261_init_params()
813 rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val); in rts5261_init_params()
815 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS; in rts5261_init_params()
816 pcr->num_slots = 1; in rts5261_init_params()
817 pcr->ops = &rts5261_pcr_ops; in rts5261_init_params()
819 pcr->flags = 0; in rts5261_init_params()
820 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5261_init_params()
821 pcr->sd30_drive_sel_1v8 = 0x00; in rts5261_init_params()
822 pcr->sd30_drive_sel_3v3 = 0x00; in rts5261_init_params()
823 pcr->aspm_en = ASPM_L1_EN; in rts5261_init_params()
824 pcr->aspm_mode = ASPM_MODE_REG; in rts5261_init_params()
825 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11); in rts5261_init_params()
826 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5261_init_params()
828 pcr->ic_version = rts5261_get_ic_version(pcr); in rts5261_init_params()
829 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl; in rts5261_init_params()
830 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl; in rts5261_init_params()
832 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3; in rts5261_init_params()