1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
44 		drive_sel = pcr->sd30_drive_sel_3v3;  in rts5261_fill_driving()
47 		drive_sel = pcr->sd30_drive_sel_1v8;  in rts5261_fill_driving()
69 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,  in rts5261_force_power_down()
75 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5261_force_power_down()
158 	struct rtsx_cr_option *option = &pcr->option;  in rts5261_card_power_on()
160 	if (option->ocp_en)  in rts5261_card_power_on()
194 	if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||  in rts5261_card_power_on()
195 	    pcr->extra_caps & EXTRA_CAPS_SD_SDR104)  in rts5261_card_power_on()
235 		return -EINVAL;  in rts5261_switch_output_voltage()
294 	if (pcr->option.ocp_en)  in rts5261_card_power_off()
302 	struct rtsx_cr_option *option = &pcr->option;  in rts5261_init_ocp()
304 	if (option->ocp_en) {  in rts5261_init_ocp()
312 			RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);  in rts5261_init_ocp()
319 		val = pcr->hw_param.ocp_glitch;  in rts5261_init_ocp()
346 	if (!pcr->option.ocp_en)  in rts5261_process_ocp()
349 	rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);  in rts5261_process_ocp()
351 	if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {  in rts5261_process_ocp()
355 		pcr->ocp_stat = 0;  in rts5261_process_ocp()
362 	struct pci_dev *pdev = pcr->pci;  in rts5261_init_from_hw()
419 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;  in rts5261_init_from_hw()
425 		pcr->extra_caps |= EXTRA_CAPS_NO_MMC;  in rts5261_init_from_hw()
427 	pcr->rtd3_en = rts5261_reg_to_rtd3(lval2);  in rts5261_init_from_hw()
430 		pcr->flags |= PCR_REVERSE_SOCKET;  in rts5261_init_from_hw()
435 	pcr->aspm_en = rts5261_reg_to_aspm(lval1);  in rts5261_init_from_hw()
436 	pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1);  in rts5261_init_from_hw()
437 	pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1);  in rts5261_init_from_hw()
457 	struct pci_dev *pdev = pcr->pci;  in rts5261_init_from_cfg()
460 	struct rtsx_cr_option *option = &pcr->option;  in rts5261_init_from_cfg()
489 	if (option->ltr_en) {  in rts5261_init_from_cfg()
494 			option->ltr_enabled = true;  in rts5261_init_from_cfg()
495 			option->ltr_active = true;  in rts5261_init_from_cfg()
496 			rtsx_set_ltr_latency(pcr, option->ltr_active_latency);  in rts5261_init_from_cfg()
498 			option->ltr_enabled = false;  in rts5261_init_from_cfg()
504 		option->force_clkreq_0 = false;  in rts5261_init_from_cfg()
506 		option->force_clkreq_0 = true;  in rts5261_init_from_cfg()
511 	struct rtsx_cr_option *option = &pcr->option;  in rts5261_extra_init_hw()
552 	if (pcr->flags & PCR_REVERSE_SOCKET)  in rts5261_extra_init_hw()
561 	if (option->force_clkreq_0)  in rts5261_extra_init_hw()
570 	if (pcr->rtd3_en) {  in rts5261_extra_init_hw()
571 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);  in rts5261_extra_init_hw()
576 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5261_extra_init_hw()
580 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);  in rts5261_extra_init_hw()
594 	if (pcr->aspm_enabled == enable)  in rts5261_enable_aspm()
597 	val |= (pcr->aspm_en & 0x02);  in rts5261_enable_aspm()
599 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,  in rts5261_enable_aspm()
600 					   PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);  in rts5261_enable_aspm()
601 	pcr->aspm_enabled = enable;  in rts5261_enable_aspm()
609 	if (pcr->aspm_enabled == enable)  in rts5261_disable_aspm()
612 	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,  in rts5261_disable_aspm()
617 	pcr->aspm_enabled = enable;  in rts5261_disable_aspm()
630 	struct rtsx_cr_option *option = &pcr->option;  in rts5261_set_l1off_cfg_sub_d0()
640 			val = option->ltr_l1off_snooze_sspwrgate;  in rts5261_set_l1off_cfg_sub_d0()
644 			val = option->ltr_l1off_sspwrgate;  in rts5261_set_l1off_cfg_sub_d0()
672 	return ((depth > 1) ? (depth - 1) : depth);  in double_ssc_depth()
711 	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",  in rts5261_pci_switch_clock()
712 		clk, pcr->cur_clock);  in rts5261_pci_switch_clock()
714 	if (clk == pcr->cur_clock)  in rts5261_pci_switch_clock()
717 	if (pcr->ops->conv_clk_and_div_n)  in rts5261_pci_switch_clock()
718 		n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);  in rts5261_pci_switch_clock()
720 		n = clk - 4;  in rts5261_pci_switch_clock()
722 		return -EINVAL;  in rts5261_pci_switch_clock()
729 	while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {  in rts5261_pci_switch_clock()
730 		if (pcr->ops->conv_clk_and_div_n) {  in rts5261_pci_switch_clock()
731 			int dbl_clk = pcr->ops->conv_clk_and_div_n(n,  in rts5261_pci_switch_clock()
733 			n = pcr->ops->conv_clk_and_div_n(dbl_clk,  in rts5261_pci_switch_clock()
736 			n = (n + 4) * 2 - 4;  in rts5261_pci_switch_clock()
741 	n = (n / 2) - 1;  in rts5261_pci_switch_clock()
751 				ssc_depth -= 1;  in rts5261_pci_switch_clock()
756 				ssc_depth -= 2;  in rts5261_pci_switch_clock()
761 				ssc_depth -= 3;  in rts5261_pci_switch_clock()
795 	/* Wait SSC clock stable */  in rts5261_pci_switch_clock()
801 	pcr->cur_clock = clk;  in rts5261_pci_switch_clock()
808 	struct rtsx_cr_option *option = &pcr->option;  in rts5261_init_params()
809 	struct rtsx_hw_param *hw_param = &pcr->hw_param;  in rts5261_init_params()
812 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;  in rts5261_init_params()
815 		pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;  in rts5261_init_params()
816 	pcr->num_slots = 1;  in rts5261_init_params()
817 	pcr->ops = &rts5261_pcr_ops;  in rts5261_init_params()
819 	pcr->flags = 0;  in rts5261_init_params()
820 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;  in rts5261_init_params()
821 	pcr->sd30_drive_sel_1v8 = 0x00;  in rts5261_init_params()
822 	pcr->sd30_drive_sel_3v3 = 0x00;  in rts5261_init_params()
823 	pcr->aspm_en = ASPM_L1_EN;  in rts5261_init_params()
824 	pcr->aspm_mode = ASPM_MODE_REG;  in rts5261_init_params()
825 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);  in rts5261_init_params()
826 	pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);  in rts5261_init_params()
828 	pcr->ic_version = rts5261_get_ic_version(pcr);  in rts5261_init_params()
829 	pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;  in rts5261_init_params()
830 	pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;  in rts5261_init_params()
832 	pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;  in rts5261_init_params()
834 	option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN  in rts5261_init_params()
836 	option->ltr_en = true;  in rts5261_init_params()
839 	option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;  in rts5261_init_params()
840 	option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;  in rts5261_init_params()
841 	option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;  in rts5261_init_params()
842 	option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;  in rts5261_init_params()
843 	option->ltr_l1off_sspwrgate = 0x7F;  in rts5261_init_params()
844 	option->ltr_l1off_snooze_sspwrgate = 0x78;  in rts5261_init_params()
846 	option->ocp_en = 1;  in rts5261_init_params()
847 	hw_param->interrupt_en |= SD_OC_INT_EN;  in rts5261_init_params()
848 	hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;  in rts5261_init_params()
849 	option->sd_800mA_ocp_thd =  RTS5261_LDO1_OCP_THD_1040;  in rts5261_init_params()