Lines Matching refs:pcr
16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) in rts5249_get_ic_version() argument
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5249_get_ic_version()
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5249_fill_driving() argument
42 drive_sel = pcr->sd30_drive_sel_3v3; in rts5249_fill_driving()
45 drive_sel = pcr->sd30_drive_sel_1v8; in rts5249_fill_driving()
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, in rts5249_fill_driving()
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, in rts5249_fill_driving()
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, in rts5249_fill_driving()
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) in rtsx_base_fetch_vendor_settings() argument
58 struct pci_dev *pdev = pcr->pci; in rtsx_base_fetch_vendor_settings()
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); in rtsx_base_fetch_vendor_settings()
65 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rtsx_base_fetch_vendor_settings()
69 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx_base_fetch_vendor_settings()
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx_base_fetch_vendor_settings()
71 pcr->card_drive_sel &= 0x3F; in rtsx_base_fetch_vendor_settings()
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); in rtsx_base_fetch_vendor_settings()
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); in rtsx_base_fetch_vendor_settings()
77 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rtsx_base_fetch_vendor_settings()
78 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg); in rtsx_base_fetch_vendor_settings()
81 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx_base_fetch_vendor_settings()
82 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); in rtsx_base_fetch_vendor_settings()
84 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx_base_fetch_vendor_settings()
87 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) in rts5249_init_from_cfg() argument
89 struct pci_dev *pdev = pcr->pci; in rts5249_init_from_cfg()
91 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_cfg()
100 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_init_from_cfg()
102 rtsx_pci_enable_oobs_polling(pcr); in rts5249_init_from_cfg()
104 rtsx_pci_disable_oobs_polling(pcr); in rts5249_init_from_cfg()
109 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); in rts5249_init_from_cfg()
112 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); in rts5249_init_from_cfg()
115 rtsx_set_dev_flag(pcr, PM_L1_1_EN); in rts5249_init_from_cfg()
118 rtsx_set_dev_flag(pcr, PM_L1_2_EN); in rts5249_init_from_cfg()
127 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5249_init_from_cfg()
134 static int rts5249_init_from_hw(struct rtsx_pcr *pcr) in rts5249_init_from_hw() argument
136 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_hw()
138 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5249_init_from_hw()
147 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) in rts52xa_force_power_down() argument
150 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rts52xa_force_power_down()
151 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rts52xa_force_power_down()
152 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, in rts52xa_force_power_down()
155 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts52xa_force_power_down()
159 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1, in rts52xa_force_power_down()
161 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); in rts52xa_force_power_down()
162 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); in rts52xa_force_power_down()
165 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN); in rts52xa_force_power_down()
168 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr) in rts52xa_save_content_from_efuse() argument
176 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
180 pcr_dbg(pcr, "Enable efuse por!"); in rts52xa_save_content_from_efuse()
181 pcr_dbg(pcr, "save efuse to autoload"); in rts52xa_save_content_from_efuse()
183 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00); in rts52xa_save_content_from_efuse()
184 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
188 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
192 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
198 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
200 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
204 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
208 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
209 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
212 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_from_efuse()
213 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
214 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_from_efuse()
215 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
220 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
223 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
225 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
229 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
233 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
234 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
236 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80); in rts52xa_save_content_from_efuse()
237 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
239 pcr_dbg(pcr, "Disable efuse por!"); in rts52xa_save_content_from_efuse()
242 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr) in rts52xa_save_content_to_autoload_space() argument
246 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val); in rts52xa_save_content_to_autoload_space()
248 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val); in rts52xa_save_content_to_autoload_space()
250 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG, in rts52xa_save_content_to_autoload_space()
253 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_to_autoload_space()
256 pcr_dbg(pcr, "Power ON efuse!"); in rts52xa_save_content_to_autoload_space()
258 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
260 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val); in rts52xa_save_content_to_autoload_space()
262 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
265 pcr_dbg(pcr, "Load from autoload"); in rts52xa_save_content_to_autoload_space()
266 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80); in rts52xa_save_content_to_autoload_space()
267 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_to_autoload_space()
268 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
269 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_to_autoload_space()
270 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
274 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) in rts5249_extra_init_hw() argument
276 struct rtsx_cr_option *option = &(pcr->option); in rts5249_extra_init_hw()
278 rts5249_init_from_cfg(pcr); in rts5249_extra_init_hw()
279 rts5249_init_from_hw(pcr); in rts5249_extra_init_hw()
281 rtsx_pci_init_cmd(pcr); in rts5249_extra_init_hw()
283 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rts5249_extra_init_hw()
284 rts52xa_save_content_to_autoload_space(pcr); in rts5249_extra_init_hw()
287 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); in rts5249_extra_init_hw()
289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); in rts5249_extra_init_hw()
291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); in rts5249_extra_init_hw()
293 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); in rts5249_extra_init_hw()
294 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); in rts5249_extra_init_hw()
296 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); in rts5249_extra_init_hw()
298 rts5249_fill_driving(pcr, OUTPUT_3V3); in rts5249_extra_init_hw()
299 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5249_extra_init_hw()
300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); in rts5249_extra_init_hw()
302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); in rts5249_extra_init_hw()
304 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); in rts5249_extra_init_hw()
306 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
307 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); in rts5249_extra_init_hw()
308 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1, in rts5249_extra_init_hw()
312 if (pcr->rtd3_en) { in rts5249_extra_init_hw()
313 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
314 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
315 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30); in rts5249_extra_init_hw()
317 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
318 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33); in rts5249_extra_init_hw()
321 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
322 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
323 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); in rts5249_extra_init_hw()
325 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30); in rts5249_extra_init_hw()
326 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
336 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
339 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
342 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); in rts5249_extra_init_hw()
343 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
344 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts5249_extra_init_hw()
346 pcr_dbg(pcr, "Power OFF efuse!"); in rts5249_extra_init_hw()
352 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) in rts5249_optimize_phy() argument
356 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); in rts5249_optimize_phy()
360 err = rtsx_pci_write_phy_register(pcr, PHY_REV, in rts5249_optimize_phy()
371 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, in rts5249_optimize_phy()
377 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts5249_optimize_phy()
384 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, in rts5249_optimize_phy()
391 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, in rts5249_optimize_phy()
398 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, in rts5249_optimize_phy()
402 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, in rts5249_optimize_phy()
406 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, in rts5249_optimize_phy()
412 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, in rts5249_optimize_phy()
418 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) in rtsx_base_turn_on_led() argument
420 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); in rtsx_base_turn_on_led()
423 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) in rtsx_base_turn_off_led() argument
425 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); in rtsx_base_turn_off_led()
428 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_enable_auto_blink() argument
430 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); in rtsx_base_enable_auto_blink()
433 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_disable_auto_blink() argument
435 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); in rtsx_base_disable_auto_blink()
438 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_on() argument
441 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_on()
444 rtsx_pci_enable_ocp(pcr); in rtsx_base_card_power_on()
446 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
447 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
449 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
451 err = rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
457 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
458 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
460 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
462 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
465 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_off() argument
467 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_off()
470 rtsx_pci_disable_ocp(pcr); in rtsx_base_card_power_off()
472 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); in rtsx_base_card_power_off()
474 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); in rtsx_base_card_power_off()
478 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rtsx_base_switch_output_voltage() argument
485 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
492 if (CHK_PCI_PID(pcr, 0x5249)) { in rtsx_base_switch_output_voltage()
493 err = rtsx_pci_update_phy(pcr, PHY_BACR, in rtsx_base_switch_output_voltage()
500 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
506 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); in rtsx_base_switch_output_voltage()
511 rtsx_pci_init_cmd(pcr); in rtsx_base_switch_output_voltage()
512 rts5249_fill_driving(pcr, voltage); in rtsx_base_switch_output_voltage()
513 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_switch_output_voltage()
581 void rts5249_init_params(struct rtsx_pcr *pcr) in rts5249_init_params() argument
583 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_params()
585 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5249_init_params()
586 pcr->num_slots = 2; in rts5249_init_params()
587 pcr->ops = &rts5249_pcr_ops; in rts5249_init_params()
589 pcr->flags = 0; in rts5249_init_params()
590 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5249_init_params()
591 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
592 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
593 pcr->aspm_en = ASPM_L1_EN; in rts5249_init_params()
594 pcr->aspm_mode = ASPM_MODE_CFG; in rts5249_init_params()
595 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); in rts5249_init_params()
596 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5249_init_params()
598 pcr->ic_version = rts5249_get_ic_version(pcr); in rts5249_init_params()
599 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; in rts5249_init_params()
600 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; in rts5249_init_params()
601 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; in rts5249_init_params()
602 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; in rts5249_init_params()
604 pcr->reg_pm_ctrl3 = PM_CTRL3; in rts5249_init_params()
620 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) in rts524a_write_phy() argument
624 return __rtsx_pci_write_phy_register(pcr, addr, val); in rts524a_write_phy()
627 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) in rts524a_read_phy() argument
631 return __rtsx_pci_read_phy_register(pcr, addr, val); in rts524a_read_phy()
634 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) in rts524a_optimize_phy() argument
638 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts524a_optimize_phy()
643 rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts524a_optimize_phy()
646 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
649 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_optimize_phy()
650 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
652 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, in rts524a_optimize_phy()
655 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, in rts524a_optimize_phy()
658 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, in rts524a_optimize_phy()
660 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, in rts524a_optimize_phy()
670 rtsx_pci_write_phy_register(pcr, PHY_ANA08, in rts524a_optimize_phy()
677 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) in rts524a_extra_init_hw() argument
679 rts5249_extra_init_hw(pcr); in rts524a_extra_init_hw()
681 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts524a_extra_init_hw()
683 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts524a_extra_init_hw()
684 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, in rts524a_extra_init_hw()
686 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts524a_extra_init_hw()
687 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_extra_init_hw()
688 rtsx_pci_write_register(pcr, LDO_DV18_CFG, in rts524a_extra_init_hw()
690 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts524a_extra_init_hw()
692 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
694 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
696 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts524a_extra_init_hw()
698 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, in rts524a_extra_init_hw()
705 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5250_set_l1off_cfg_sub_d0() argument
707 struct rtsx_cr_option *option = &(pcr->option); in rts5250_set_l1off_cfg_sub_d0()
709 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); in rts5250_set_l1off_cfg_sub_d0()
714 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5250_set_l1off_cfg_sub_d0()
715 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5250_set_l1off_cfg_sub_d0()
728 if (rtsx_check_dev_flag(pcr, in rts5250_set_l1off_cfg_sub_d0()
736 rtsx_set_l1off_sub(pcr, val); in rts5250_set_l1off_cfg_sub_d0()
756 void rts524a_init_params(struct rtsx_pcr *pcr) in rts524a_init_params() argument
758 rts5249_init_params(pcr); in rts524a_init_params()
759 pcr->aspm_mode = ASPM_MODE_REG; in rts524a_init_params()
760 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); in rts524a_init_params()
761 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts524a_init_params()
762 pcr->option.ltr_l1off_snooze_sspwrgate = in rts524a_init_params()
765 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts524a_init_params()
766 pcr->ops = &rts524a_pcr_ops; in rts524a_init_params()
768 pcr->option.ocp_en = 1; in rts524a_init_params()
769 if (pcr->option.ocp_en) in rts524a_init_params()
770 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts524a_init_params()
771 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts524a_init_params()
772 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; in rts524a_init_params()
776 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) in rts525a_card_power_on() argument
778 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts525a_card_power_on()
780 return rtsx_base_card_power_on(pcr, card); in rts525a_card_power_on()
783 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts525a_switch_output_voltage() argument
787 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
789 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); in rts525a_switch_output_voltage()
792 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
794 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, in rts525a_switch_output_voltage()
801 rtsx_pci_init_cmd(pcr); in rts525a_switch_output_voltage()
802 rts5249_fill_driving(pcr, voltage); in rts525a_switch_output_voltage()
803 return rtsx_pci_send_cmd(pcr, 100); in rts525a_switch_output_voltage()
806 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) in rts525a_optimize_phy() argument
810 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts525a_optimize_phy()
815 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, in rts525a_optimize_phy()
820 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, in rts525a_optimize_phy()
824 if (is_version(pcr, 0x525A, IC_VER_A)) in rts525a_optimize_phy()
825 rtsx_pci_write_phy_register(pcr, _PHY_REV0, in rts525a_optimize_phy()
832 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) in rts525a_extra_init_hw() argument
834 rts5249_extra_init_hw(pcr); in rts525a_extra_init_hw()
836 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD); in rts525a_extra_init_hw()
838 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts525a_extra_init_hw()
839 if (is_version(pcr, 0x525A, IC_VER_A)) { in rts525a_extra_init_hw()
840 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, in rts525a_extra_init_hw()
842 rtsx_pci_write_register(pcr, RREF_CFG, in rts525a_extra_init_hw()
844 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts525a_extra_init_hw()
846 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts525a_extra_init_hw()
848 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, in rts525a_extra_init_hw()
850 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, in rts525a_extra_init_hw()
852 rtsx_pci_write_register(pcr, OOBS_CONFIG, in rts525a_extra_init_hw()
874 void rts525a_init_params(struct rtsx_pcr *pcr) in rts525a_init_params() argument
876 rts5249_init_params(pcr); in rts525a_init_params()
877 pcr->aspm_mode = ASPM_MODE_REG; in rts525a_init_params()
878 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); in rts525a_init_params()
879 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts525a_init_params()
880 pcr->option.ltr_l1off_snooze_sspwrgate = in rts525a_init_params()
883 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts525a_init_params()
884 pcr->ops = &rts525a_pcr_ops; in rts525a_init_params()
886 pcr->option.ocp_en = 1; in rts525a_init_params()
887 if (pcr->option.ocp_en) in rts525a_init_params()
888 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts525a_init_params()
889 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts525a_init_params()
890 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; in rts525a_init_params()