Lines Matching +full:ssc +full:- +full:internal
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
45 drive_sel = pcr->sd30_drive_sel_3v3; in rts5228_fill_driving()
48 drive_sel = pcr->sd30_drive_sel_1v8; in rts5228_fill_driving()
63 struct pci_dev *pdev = pcr->pci; in rtsx5228_fetch_vendor_settings()
74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx5228_fetch_vendor_settings()
75 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx5228_fetch_vendor_settings()
81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg); in rtsx5228_fetch_vendor_settings()
83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx5228_fetch_vendor_settings()
84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); in rtsx5228_fetch_vendor_settings()
86 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx5228_fetch_vendor_settings()
102 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5228_force_power_down()
108 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5228_force_power_down()
181 struct rtsx_cr_option *option = &pcr->option; in rts5228_card_power_on()
183 if (option->ocp_en) in rts5228_card_power_on()
222 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || in rts5228_card_power_on()
223 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) in rts5228_card_power_on()
263 return -EINVAL; in rts5228_switch_output_voltage()
318 if (pcr->option.ocp_en) in rts5228_card_power_off()
326 struct rtsx_cr_option *option = &pcr->option; in rts5228_init_ocp()
328 if (option->ocp_en) { in rts5228_init_ocp()
336 RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd); in rts5228_init_ocp()
345 val = pcr->hw_param.ocp_glitch; in rts5228_init_ocp()
373 if (!pcr->option.ocp_en) in rts5228_process_ocp()
376 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); in rts5228_process_ocp()
378 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { in rts5228_process_ocp()
382 pcr->ocp_stat = 0; in rts5228_process_ocp()
389 struct pci_dev *pdev = pcr->pci; in rts5228_init_from_cfg()
392 struct rtsx_cr_option *option = &pcr->option; in rts5228_init_from_cfg()
426 if (option->ltr_en) { in rts5228_init_from_cfg()
429 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); in rts5228_init_from_cfg()
431 option->ltr_enabled = true; in rts5228_init_from_cfg()
432 option->ltr_active = true; in rts5228_init_from_cfg()
433 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5228_init_from_cfg()
435 option->ltr_enabled = false; in rts5228_init_from_cfg()
441 option->force_clkreq_0 = false; in rts5228_init_from_cfg()
443 option->force_clkreq_0 = true; in rts5228_init_from_cfg()
448 struct rtsx_cr_option *option = &pcr->option; in rts5228_extra_init_hw()
474 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5228_extra_init_hw()
483 if (option->force_clkreq_0) in rts5228_extra_init_hw()
492 if (pcr->rtd3_en) { in rts5228_extra_init_hw()
493 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01); in rts5228_extra_init_hw()
498 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5228_extra_init_hw()
502 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00); in rts5228_extra_init_hw()
511 if (pcr->aspm_enabled == enable) in rts5228_enable_aspm()
516 val |= (pcr->aspm_en & 0x02); in rts5228_enable_aspm()
518 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5228_enable_aspm()
519 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); in rts5228_enable_aspm()
520 pcr->aspm_enabled = enable; in rts5228_enable_aspm()
527 if (pcr->aspm_enabled == enable) in rts5228_disable_aspm()
530 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rts5228_disable_aspm()
537 pcr->aspm_enabled = enable; in rts5228_disable_aspm()
550 struct rtsx_cr_option *option = &pcr->option; in rts5228_set_l1off_cfg_sub_d0()
560 val = option->ltr_l1off_snooze_sspwrgate; in rts5228_set_l1off_cfg_sub_d0()
564 val = option->ltr_l1off_sspwrgate; in rts5228_set_l1off_cfg_sub_d0()
595 return ((depth > 1) ? (depth - 1) : depth); in double_ssc_depth()
629 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", in rts5228_pci_switch_clock()
630 clk, pcr->cur_clock); in rts5228_pci_switch_clock()
632 if (clk == pcr->cur_clock) in rts5228_pci_switch_clock()
635 if (pcr->ops->conv_clk_and_div_n) in rts5228_pci_switch_clock()
636 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); in rts5228_pci_switch_clock()
638 n = clk - 4; in rts5228_pci_switch_clock()
640 return -EINVAL; in rts5228_pci_switch_clock()
647 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5228_pci_switch_clock()
648 if (pcr->ops->conv_clk_and_div_n) { in rts5228_pci_switch_clock()
649 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, in rts5228_pci_switch_clock()
651 n = pcr->ops->conv_clk_and_div_n(dbl_clk, in rts5228_pci_switch_clock()
654 n = (n + 4) * 2 - 4; in rts5228_pci_switch_clock()
659 n = (n / 2) - 1; in rts5228_pci_switch_clock()
669 ssc_depth -= 1; in rts5228_pci_switch_clock()
674 ssc_depth -= 2; in rts5228_pci_switch_clock()
679 ssc_depth -= 3; in rts5228_pci_switch_clock()
713 /* Wait SSC clock stable */ in rts5228_pci_switch_clock()
719 pcr->cur_clock = clk; in rts5228_pci_switch_clock()
726 struct rtsx_cr_option *option = &pcr->option; in rts5228_init_params()
727 struct rtsx_hw_param *hw_param = &pcr->hw_param; in rts5228_init_params()
729 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5228_init_params()
730 pcr->num_slots = 1; in rts5228_init_params()
731 pcr->ops = &rts5228_pcr_ops; in rts5228_init_params()
733 pcr->flags = 0; in rts5228_init_params()
734 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5228_init_params()
735 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; in rts5228_init_params()
736 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; in rts5228_init_params()
737 pcr->aspm_en = ASPM_L1_EN; in rts5228_init_params()
738 pcr->aspm_mode = ASPM_MODE_REG; in rts5228_init_params()
739 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); in rts5228_init_params()
740 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5228_init_params()
742 pcr->ic_version = rts5228_get_ic_version(pcr); in rts5228_init_params()
743 pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl; in rts5228_init_params()
744 pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl; in rts5228_init_params()
746 pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3; in rts5228_init_params()
748 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN in rts5228_init_params()
750 option->ltr_en = true; in rts5228_init_params()
753 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; in rts5228_init_params()
754 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; in rts5228_init_params()
755 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; in rts5228_init_params()
756 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; in rts5228_init_params()
757 option->ltr_l1off_sspwrgate = 0x7F; in rts5228_init_params()
758 option->ltr_l1off_snooze_sspwrgate = 0x78; in rts5228_init_params()
760 option->ocp_en = 1; in rts5228_init_params()
761 hw_param->interrupt_en |= SD_OC_INT_EN; in rts5228_init_params()
762 hw_param->ocp_glitch = SD_OCP_GLITCH_800U; in rts5228_init_params()
763 option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930; in rts5228_init_params()