Lines Matching refs:divsel
504 u32 divsel; member
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1349 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1503 u32 divsel; in dsiclk_rate() local
1506 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()
1507 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1509 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()
1510 divsel = dsiclk[n].divsel; in dsiclk_rate()
1512 dsiclk[n].divsel = divsel; in dsiclk_rate()
1514 switch (divsel) { in dsiclk_rate()
1881 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : in set_dsiclk_rate()
1887 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); in set_dsiclk_rate()