Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
88 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
92 iowrite16(value, asic->mapping + in asic3_write_register()
93 (reg >> asic->bus_shift)); in asic3_write_register()
99 return ioread16(asic->mapping + in asic3_read_register()
100 (reg >> asic->bus_shift)); in asic3_read_register()
109 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
116 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
127 u16 edge; in asic3_irq_flip_edge() local
130 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_irq_flip_edge()
131 edge = asic3_read_register(asic, in asic3_irq_flip_edge()
133 edge ^= bit; in asic3_irq_flip_edge()
135 base + ASIC3_GPIO_EDGE_TRIGGER, edge); in asic3_irq_flip_edge()
136 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_flip_edge()
146 data->chip->irq_ack(data); in asic3_irq_demux()
152 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
155 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
168 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
176 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
185 irqnr = asic->irq_base + in asic3_irq_demux()
189 if (asic->irq_bothedge[bank] & bit) in asic3_irq_demux()
199 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) in asic3_irq_demux()
200 generic_handle_irq(asic->irq_base + i); in asic3_irq_demux()
205 dev_err(asic->dev, "interrupt processing overrun\n"); in asic3_irq_demux()
212 n = (irq - asic->irq_base) >> 4; in asic3_irq_to_bank()
214 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)); in asic3_irq_to_bank()
219 return (irq - asic->irq_base) & 0xf; in asic3_irq_to_index()
228 bank = asic3_irq_to_bank(asic, data->irq); in asic3_mask_gpio_irq()
229 index = asic3_irq_to_index(asic, data->irq); in asic3_mask_gpio_irq()
231 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_mask_gpio_irq()
235 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_gpio_irq()
244 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_mask_irq()
250 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_mask_irq()
256 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_irq()
265 bank = asic3_irq_to_bank(asic, data->irq); in asic3_unmask_gpio_irq()
266 index = asic3_irq_to_index(asic, data->irq); in asic3_unmask_gpio_irq()
268 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_gpio_irq()
272 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_gpio_irq()
281 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_irq()
287 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_unmask_irq()
293 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_irq()
300 u16 trigger, level, edge, bit; in asic3_gpio_irq_type() local
303 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_type()
304 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_type()
307 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_irq_type()
310 edge = asic3_read_register(asic, in asic3_gpio_irq_type()
314 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; in asic3_gpio_irq_type()
318 edge |= bit; in asic3_gpio_irq_type()
321 edge &= ~bit; in asic3_gpio_irq_type()
324 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) in asic3_gpio_irq_type()
325 edge &= ~bit; in asic3_gpio_irq_type()
327 edge |= bit; in asic3_gpio_irq_type()
328 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; in asic3_gpio_irq_type()
341 dev_notice(asic->dev, "irq type not changed\n"); in asic3_gpio_irq_type()
346 edge); in asic3_gpio_irq_type()
349 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_irq_type()
359 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_set_wake()
360 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_set_wake()
369 .name = "ASIC3-GPIO",
394 asic->irq_nr = ret; in asic3_irq_probe()
401 irq_base = asic->irq_base; in asic3_irq_probe()
404 if (irq < asic->irq_base + ASIC3_NUM_GPIOS) in asic3_irq_probe()
417 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic); in asic3_irq_probe()
418 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); in asic3_irq_probe()
428 irq_base = asic->irq_base; in asic3_irq_remove()
435 irq_set_chained_handler(asic->irq_nr, NULL); in asic3_irq_remove()
440 unsigned offset, int out) in asic3_gpio_direction() argument
442 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; in asic3_gpio_direction()
448 gpio_base = ASIC3_GPIO_TO_BASE(offset); in asic3_gpio_direction()
451 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_direction()
452 gpio_base, offset); in asic3_gpio_direction()
453 return -EINVAL; in asic3_gpio_direction()
456 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_direction()
468 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_direction()
475 unsigned offset) in asic3_gpio_direction_input() argument
477 return asic3_gpio_direction(chip, offset, 0); in asic3_gpio_direction_input()
481 unsigned offset, int value) in asic3_gpio_direction_output() argument
483 return asic3_gpio_direction(chip, offset, 1); in asic3_gpio_direction_output()
487 unsigned offset) in asic3_gpio_get() argument
490 u32 mask = ASIC3_GPIO_TO_MASK(offset); in asic3_gpio_get()
494 gpio_base = ASIC3_GPIO_TO_BASE(offset); in asic3_gpio_get()
497 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_get()
498 gpio_base, offset); in asic3_gpio_get()
499 return -EINVAL; in asic3_gpio_get()
507 unsigned offset, int value) in asic3_gpio_set() argument
515 gpio_base = ASIC3_GPIO_TO_BASE(offset); in asic3_gpio_set()
518 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_set()
519 gpio_base, offset); in asic3_gpio_set()
523 mask = ASIC3_GPIO_TO_MASK(offset); in asic3_gpio_set()
525 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_set()
536 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_set()
539 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset) in asic3_gpio_to_irq() argument
543 return asic->irq_base + offset; in asic3_gpio_to_irq()
596 return gpiochip_add_data(&asic->gpio, asic); in asic3_gpio_probe()
603 gpiochip_remove(&asic->gpio); in asic3_gpio_remove()
611 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_clk_enable()
612 if (clk->enabled++ == 0) { in asic3_clk_enable()
614 cdex |= clk->cdex; in asic3_clk_enable()
617 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_enable()
625 WARN_ON(clk->enabled == 0); in asic3_clk_disable()
627 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_clk_disable()
628 if (--clk->enabled == 0) { in asic3_clk_disable()
630 cdex &= ~clk->cdex; in asic3_clk_disable()
633 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_disable()
657 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_enable()
660 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_enable()
661 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_enable()
662 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_enable()
681 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_disable()
686 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_disable()
687 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_disable()
688 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_disable()
705 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_pwr()
707 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_pwr()
712 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_clk_div()
714 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_clk_div()
731 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_enable()
733 /* Not sure if it must be done bit by bit, but leaving as-is */ in asic3_mmc_enable()
743 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_enable()
747 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_enable()
754 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_enable()
755 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_enable()
765 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */ in asic3_mmc_enable()
766 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, in asic3_mmc_enable()
774 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_disable()
781 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_disable()
782 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_disable()
783 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_disable()
784 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_disable()
789 .name = "tmio-mmc",
809 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_enable()
811 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_enable()
819 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_disable()
821 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_disable()
829 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_suspend()
831 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) in asic3_leds_suspend()
834 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_suspend()
841 .name = "leds-asic3",
849 .name = "leds-asic3",
857 .name = "leds-asic3",
876 dev_dbg(asic->dev, "no SDIO MEM resource\n"); in asic3_mfd_probe()
880 dev_dbg(asic->dev, "no SDIO IRQ resource\n"); in asic3_mfd_probe()
886 ds1wm_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
887 ds1wm_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
891 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> in asic3_mfd_probe()
892 asic->bus_shift) + mem_sdio->start, in asic3_mfd_probe()
893 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift); in asic3_mfd_probe()
894 if (!asic->tmio_cnf) { in asic3_mfd_probe()
895 ret = -ENOMEM; in asic3_mfd_probe()
896 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); in asic3_mfd_probe()
900 asic3_mmc_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
901 asic3_mmc_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
903 if (pdata->clock_rate) { in asic3_mfd_probe()
904 ds1wm_pdata.clock_rate = pdata->clock_rate; in asic3_mfd_probe()
905 ret = mfd_add_devices(&pdev->dev, pdev->id, in asic3_mfd_probe()
906 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL); in asic3_mfd_probe()
912 ret = mfd_add_devices(&pdev->dev, pdev->id, in asic3_mfd_probe()
919 if (pdata->leds) { in asic3_mfd_probe()
923 asic3_cell_leds[i].platform_data = &pdata->leds[i]; in asic3_mfd_probe()
924 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]); in asic3_mfd_probe()
926 ret = mfd_add_devices(&pdev->dev, 0, in asic3_mfd_probe()
932 if (asic->tmio_cnf) in asic3_mfd_probe()
933 iounmap(asic->tmio_cnf); in asic3_mfd_probe()
942 mfd_remove_devices(&pdev->dev); in asic3_mfd_remove()
943 iounmap(asic->tmio_cnf); in asic3_mfd_remove()
949 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev); in asic3_probe()
955 asic = devm_kzalloc(&pdev->dev, in asic3_probe()
958 return -ENOMEM; in asic3_probe()
960 raw_spin_lock_init(&asic->lock); in asic3_probe()
962 asic->dev = &pdev->dev; in asic3_probe()
966 dev_err(asic->dev, "no MEM resource\n"); in asic3_probe()
967 return -ENOMEM; in asic3_probe()
970 asic->mapping = ioremap(mem->start, resource_size(mem)); in asic3_probe()
971 if (!asic->mapping) { in asic3_probe()
972 dev_err(asic->dev, "Couldn't ioremap\n"); in asic3_probe()
973 return -ENOMEM; in asic3_probe()
976 asic->irq_base = pdata->irq_base; in asic3_probe()
979 asic->bus_shift = 2 - (resource_size(mem) >> 12); in asic3_probe()
986 dev_err(asic->dev, "Couldn't probe IRQs\n"); in asic3_probe()
990 asic->gpio.label = "asic3"; in asic3_probe()
991 asic->gpio.base = pdata->gpio_base; in asic3_probe()
992 asic->gpio.ngpio = ASIC3_NUM_GPIOS; in asic3_probe()
993 asic->gpio.get = asic3_gpio_get; in asic3_probe()
994 asic->gpio.set = asic3_gpio_set; in asic3_probe()
995 asic->gpio.direction_input = asic3_gpio_direction_input; in asic3_probe()
996 asic->gpio.direction_output = asic3_gpio_direction_output; in asic3_probe()
997 asic->gpio.to_irq = asic3_gpio_to_irq; in asic3_probe()
1000 pdata->gpio_config, in asic3_probe()
1001 pdata->gpio_config_num); in asic3_probe()
1003 dev_err(asic->dev, "GPIO probe failed\n"); in asic3_probe()
1007 /* Making a per-device copy is only needed for the in asic3_probe()
1010 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); in asic3_probe()
1017 dev_info(asic->dev, "ASIC3 Core driver\n"); in asic3_probe()
1025 iounmap(asic->mapping); in asic3_probe()
1045 iounmap(asic->mapping); in asic3_remove()