Lines Matching refs:ldr
45 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
46 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
49 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
52 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
55 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
58 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
61 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
64 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
67 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
70 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
73 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
76 ldr r1, [r0, #EMIF_COS_CONFIG]
79 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
82 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
85 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
88 ldr r1, [r0, #EMIF_OCP_CONFIG]
91 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
95 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
98 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
101 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
104 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
107 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
110 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
118 ldr r1, [r3, r5]
137 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
138 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
141 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
145 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
149 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
153 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
157 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
161 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
164 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
167 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
170 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
173 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
176 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
179 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
182 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
186 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
189 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
192 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
195 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
198 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
201 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
204 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
215 ldr r1, [r3, r5]
228 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
232 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
248 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
250 ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
252 ldr r2, [r0, #EMIF_SDRAM_CONFIG]
272 2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
291 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
292 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
294 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
311 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
312 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
322 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
330 1: ldr r1, [r0, #EMIF_STATUS]
348 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
349 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
351 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
356 1: ldr r1, [r0, #EMIF_STATUS]