Lines Matching full:r2
46 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
50 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
53 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
56 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
59 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
62 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
65 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
68 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
71 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
74 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
77 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
80 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
83 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
86 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
89 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
96 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
99 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
102 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
105 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
108 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
111 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
115 add r4, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
138 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
141 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
145 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
149 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
153 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
157 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
161 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
164 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
167 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
170 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
173 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
176 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
179 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
186 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
189 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
192 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
195 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
198 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
201 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
204 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
212 add r3, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
228 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
232 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
233 and r2, r1, #SDRAM_TYPE_MASK
234 cmp r2, #EMIF_SDCFG_TYPE_DDR2
252 ldr r2, [r0, #EMIF_SDRAM_CONFIG]
253 and r2, r2, #SDRAM_TYPE_MASK
254 cmp r2, #EMIF_SDCFG_TYPE_DDR3
266 mov r2, #0x2000
268 subs r2, r2, #0x1
292 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
312 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
322 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
349 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
351 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]