Lines Matching refs:num_timings
367 unsigned int num_timings; member
443 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
508 for (i = 0; i < mc->num_timings; i++) { in emc_prepare_mc_clk_cfg()
961 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
963 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
967 for (i = 0; i < mc->num_timings; i++) { in emc_check_mc_timings()
998 emc->num_timings = child_count; in emc_load_timings_from_dt()
1009 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
1018 emc->num_timings, in emc_load_timings_from_dt()
1021 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
1202 if (!emc->num_timings) in emc_round_rate()
1205 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
1207 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
1208 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
1340 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1353 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1446 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
1454 if (!emc->num_timings) { in tegra_emc_debugfs_init()