Lines Matching full:mc
21 #include "mc.h"
25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
43 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
46 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
49 { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
57 struct tegra_mc *mc = data; in tegra_mc_devm_action_put_device() local
59 put_device(mc->dev); in tegra_mc_devm_action_put_device()
75 struct tegra_mc *mc; in devm_tegra_memory_controller_get() local
87 mc = platform_get_drvdata(pdev); in devm_tegra_memory_controller_get()
88 if (!mc) { in devm_tegra_memory_controller_get()
93 err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc); in devm_tegra_memory_controller_get()
97 return mc; in devm_tegra_memory_controller_get()
101 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) in tegra_mc_probe_device() argument
103 if (mc->soc->ops && mc->soc->ops->probe_device) in tegra_mc_probe_device()
104 return mc->soc->ops->probe_device(mc, dev); in tegra_mc_probe_device()
110 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument
116 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_block_dma_common()
118 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
119 mc_writel(mc, value, rst->control); in tegra_mc_block_dma_common()
121 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_block_dma_common()
126 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, in tegra_mc_dma_idling_common() argument
129 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in tegra_mc_dma_idling_common()
132 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, in tegra_mc_unblock_dma_common() argument
138 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_unblock_dma_common()
140 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in tegra_mc_unblock_dma_common()
141 mc_writel(mc, value, rst->control); in tegra_mc_unblock_dma_common()
143 spin_unlock_irqrestore(&mc->lock, flags); in tegra_mc_unblock_dma_common()
148 static int tegra_mc_reset_status_common(struct tegra_mc *mc, in tegra_mc_reset_status_common() argument
151 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in tegra_mc_reset_status_common()
166 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, in tegra_mc_reset_find() argument
171 for (i = 0; i < mc->soc->num_resets; i++) in tegra_mc_reset_find()
172 if (mc->soc->resets[i].id == id) in tegra_mc_reset_find()
173 return &mc->soc->resets[i]; in tegra_mc_reset_find()
181 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_assert() local
187 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_assert()
191 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_assert()
198 if (rst_ops->reset_status(mc, rst)) in tegra_mc_hotreset_assert()
204 err = rst_ops->block_dma(mc, rst); in tegra_mc_hotreset_assert()
206 dev_err(mc->dev, "failed to block %s DMA: %d\n", in tegra_mc_hotreset_assert()
214 while (!rst_ops->dma_idling(mc, rst)) { in tegra_mc_hotreset_assert()
216 dev_err(mc->dev, "failed to flush %s DMA\n", in tegra_mc_hotreset_assert()
227 err = rst_ops->hotreset_assert(mc, rst); in tegra_mc_hotreset_assert()
229 dev_err(mc->dev, "failed to hot reset %s: %d\n", in tegra_mc_hotreset_assert()
241 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_deassert() local
246 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_deassert()
250 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_deassert()
256 err = rst_ops->hotreset_deassert(mc, rst); in tegra_mc_hotreset_deassert()
258 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", in tegra_mc_hotreset_deassert()
266 err = rst_ops->unblock_dma(mc, rst); in tegra_mc_hotreset_deassert()
268 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", in tegra_mc_hotreset_deassert()
280 struct tegra_mc *mc = reset_to_mc(rcdev); in tegra_mc_hotreset_status() local
284 rst = tegra_mc_reset_find(mc, id); in tegra_mc_hotreset_status()
288 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_status()
292 return rst_ops->reset_status(mc, rst); in tegra_mc_hotreset_status()
301 static int tegra_mc_reset_setup(struct tegra_mc *mc) in tegra_mc_reset_setup() argument
305 mc->reset.ops = &tegra_mc_reset_ops; in tegra_mc_reset_setup()
306 mc->reset.owner = THIS_MODULE; in tegra_mc_reset_setup()
307 mc->reset.of_node = mc->dev->of_node; in tegra_mc_reset_setup()
308 mc->reset.of_reset_n_cells = 1; in tegra_mc_reset_setup()
309 mc->reset.nr_resets = mc->soc->num_resets; in tegra_mc_reset_setup()
311 err = reset_controller_register(&mc->reset); in tegra_mc_reset_setup()
318 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) in tegra_mc_write_emem_configuration() argument
323 for (i = 0; i < mc->num_timings; i++) { in tegra_mc_write_emem_configuration()
324 if (mc->timings[i].rate == rate) { in tegra_mc_write_emem_configuration()
325 timing = &mc->timings[i]; in tegra_mc_write_emem_configuration()
331 dev_err(mc->dev, "no memory timing registered for rate %lu\n", in tegra_mc_write_emem_configuration()
336 for (i = 0; i < mc->soc->num_emem_regs; ++i) in tegra_mc_write_emem_configuration()
337 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
343 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) in tegra_mc_get_emem_device_count() argument
347 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); in tegra_mc_get_emem_device_count()
360 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) in tegra_mc_setup_latency_allowance() argument
366 /* compute the number of MC clock cycles per tick */ in tegra_mc_setup_latency_allowance()
367 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); in tegra_mc_setup_latency_allowance()
370 value = mc_readl(mc, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
373 mc_writel(mc, value, MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
376 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_setup_latency_allowance()
377 const struct tegra_mc_client *client = &mc->soc->clients[i]; in tegra_mc_setup_latency_allowance()
380 value = mc_readl(mc, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
383 mc_writel(mc, value, client->regs.la.reg); in tegra_mc_setup_latency_allowance()
387 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in tegra_mc_setup_latency_allowance()
392 static int load_one_timing(struct tegra_mc *mc, in load_one_timing() argument
401 dev_err(mc->dev, in load_one_timing()
407 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, in load_one_timing()
414 mc->soc->num_emem_regs); in load_one_timing()
416 dev_err(mc->dev, in load_one_timing()
425 static int load_timings(struct tegra_mc *mc, struct device_node *node) in load_timings() argument
432 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), in load_timings()
434 if (!mc->timings) in load_timings()
437 mc->num_timings = child_count; in load_timings()
440 timing = &mc->timings[i++]; in load_timings()
442 err = load_one_timing(mc, timing, child); in load_timings()
452 static int tegra_mc_setup_timings(struct tegra_mc *mc) in tegra_mc_setup_timings() argument
460 mc->num_timings = 0; in tegra_mc_setup_timings()
462 for_each_child_of_node(mc->dev->of_node, node) { in tegra_mc_setup_timings()
468 err = load_timings(mc, node); in tegra_mc_setup_timings()
475 if (mc->num_timings == 0) in tegra_mc_setup_timings()
476 dev_warn(mc->dev, in tegra_mc_setup_timings()
483 int tegra30_mc_probe(struct tegra_mc *mc) in tegra30_mc_probe() argument
487 mc->clk = devm_clk_get_optional(mc->dev, "mc"); in tegra30_mc_probe()
488 if (IS_ERR(mc->clk)) { in tegra30_mc_probe()
489 dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk)); in tegra30_mc_probe()
490 return PTR_ERR(mc->clk); in tegra30_mc_probe()
494 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); in tegra30_mc_probe()
496 err = tegra_mc_setup_latency_allowance(mc); in tegra30_mc_probe()
498 dev_err(mc->dev, "failed to setup latency allowance: %d\n", err); in tegra30_mc_probe()
502 err = tegra_mc_setup_timings(mc); in tegra30_mc_probe()
504 dev_err(mc->dev, "failed to setup timings: %d\n", err); in tegra30_mc_probe()
517 static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status, in mc_global_intstatus_to_channel() argument
520 if ((status & mc->soc->ch_intmask) == 0) in mc_global_intstatus_to_channel()
523 *mc_channel = __ffs((status & mc->soc->ch_intmask) >> in mc_global_intstatus_to_channel()
524 mc->soc->global_intstatus_channel_shift); in mc_global_intstatus_to_channel()
529 static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc, in mc_channel_to_global_intstatus() argument
532 return BIT(channel) << mc->soc->global_intstatus_channel_shift; in mc_channel_to_global_intstatus()
537 struct tegra_mc *mc = data; in tegra30_mc_handle_irq() local
541 if (mc->soc->num_channels) { in tegra30_mc_handle_irq()
545 global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS); in tegra30_mc_handle_irq()
546 err = mc_global_intstatus_to_channel(mc, global_status, &channel); in tegra30_mc_handle_irq()
548 dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", in tegra30_mc_handle_irq()
554 status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask; in tegra30_mc_handle_irq()
556 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra30_mc_handle_irq()
608 if (mc->soc->has_addr_hi_reg) in tegra30_mc_handle_irq()
614 if (mc->soc->num_channels) in tegra30_mc_handle_irq()
615 value = mc_ch_readl(mc, channel, status_reg); in tegra30_mc_handle_irq()
617 value = mc_readl(mc, status_reg); in tegra30_mc_handle_irq()
620 if (mc->soc->num_address_bits > 32) { in tegra30_mc_handle_irq()
622 if (mc->soc->num_channels) in tegra30_mc_handle_irq()
623 addr = mc_ch_readl(mc, channel, addr_hi_reg); in tegra30_mc_handle_irq()
625 addr = mc_readl(mc, addr_hi_reg); in tegra30_mc_handle_irq()
644 id = value & mc->soc->client_id_mask; in tegra30_mc_handle_irq()
646 for (i = 0; i < mc->soc->num_clients; i++) { in tegra30_mc_handle_irq()
647 if (mc->soc->clients[i].id == id) { in tegra30_mc_handle_irq()
648 client = mc->soc->clients[i].name; in tegra30_mc_handle_irq()
686 if (mc->soc->num_channels) in tegra30_mc_handle_irq()
687 value = mc_ch_readl(mc, channel, addr_reg); in tegra30_mc_handle_irq()
689 value = mc_readl(mc, addr_reg); in tegra30_mc_handle_irq()
692 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", in tegra30_mc_handle_irq()
698 if (mc->soc->num_channels) { in tegra30_mc_handle_irq()
699 mc_ch_writel(mc, channel, status, MC_INTSTATUS); in tegra30_mc_handle_irq()
700 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, in tegra30_mc_handle_irq()
701 mc_channel_to_global_intstatus(mc, channel), in tegra30_mc_handle_irq()
704 mc_writel(mc, status, MC_INTSTATUS); in tegra30_mc_handle_irq()
733 * Memory Controller (MC) has few Memory Clients that are issuing memory
734 * bandwidth allocation requests to the MC interconnect provider. The MC
738 * to the required bandwidth. Each MC interconnect node represents an
748 * ... | MC +--->+ EMC +--->+ EMEM |
755 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) in tegra_mc_interconnect_setup() argument
762 if (!device_property_present(mc->dev, "#interconnect-cells") || in tegra_mc_interconnect_setup()
763 !mc->soc->icc_ops) in tegra_mc_interconnect_setup()
766 mc->provider.dev = mc->dev; in tegra_mc_interconnect_setup()
767 mc->provider.data = &mc->provider; in tegra_mc_interconnect_setup()
768 mc->provider.set = mc->soc->icc_ops->set; in tegra_mc_interconnect_setup()
769 mc->provider.aggregate = mc->soc->icc_ops->aggregate; in tegra_mc_interconnect_setup()
770 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; in tegra_mc_interconnect_setup()
772 err = icc_provider_add(&mc->provider); in tegra_mc_interconnect_setup()
784 icc_node_add(node, &mc->provider); in tegra_mc_interconnect_setup()
791 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_interconnect_setup()
792 /* create MC client node */ in tegra_mc_interconnect_setup()
793 node = icc_node_create(mc->soc->clients[i].id); in tegra_mc_interconnect_setup()
799 node->name = mc->soc->clients[i].name; in tegra_mc_interconnect_setup()
800 icc_node_add(node, &mc->provider); in tegra_mc_interconnect_setup()
811 icc_nodes_remove(&mc->provider); in tegra_mc_interconnect_setup()
813 icc_provider_del(&mc->provider); in tegra_mc_interconnect_setup()
820 struct tegra_mc *mc; in tegra_mc_probe() local
824 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); in tegra_mc_probe()
825 if (!mc) in tegra_mc_probe()
828 platform_set_drvdata(pdev, mc); in tegra_mc_probe()
829 spin_lock_init(&mc->lock); in tegra_mc_probe()
830 mc->soc = of_device_get_match_data(&pdev->dev); in tegra_mc_probe()
831 mc->dev = &pdev->dev; in tegra_mc_probe()
833 mask = DMA_BIT_MASK(mc->soc->num_address_bits); in tegra_mc_probe()
841 /* length of MC tick in nanoseconds */ in tegra_mc_probe()
842 mc->tick = 30; in tegra_mc_probe()
844 mc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_mc_probe()
845 if (IS_ERR(mc->regs)) in tegra_mc_probe()
846 return PTR_ERR(mc->regs); in tegra_mc_probe()
848 mc->debugfs.root = debugfs_create_dir("mc", NULL); in tegra_mc_probe()
850 if (mc->soc->ops && mc->soc->ops->probe) { in tegra_mc_probe()
851 err = mc->soc->ops->probe(mc); in tegra_mc_probe()
856 if (mc->soc->ops && mc->soc->ops->handle_irq) { in tegra_mc_probe()
857 mc->irq = platform_get_irq(pdev, 0); in tegra_mc_probe()
858 if (mc->irq < 0) in tegra_mc_probe()
859 return mc->irq; in tegra_mc_probe()
861 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); in tegra_mc_probe()
863 if (mc->soc->num_channels) in tegra_mc_probe()
864 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, in tegra_mc_probe()
867 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
869 err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, in tegra_mc_probe()
870 dev_name(&pdev->dev), mc); in tegra_mc_probe()
872 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, in tegra_mc_probe()
878 if (mc->soc->reset_ops) { in tegra_mc_probe()
879 err = tegra_mc_reset_setup(mc); in tegra_mc_probe()
884 err = tegra_mc_interconnect_setup(mc); in tegra_mc_probe()
889 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { in tegra_mc_probe()
890 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); in tegra_mc_probe()
891 if (IS_ERR(mc->smmu)) { in tegra_mc_probe()
893 PTR_ERR(mc->smmu)); in tegra_mc_probe()
894 mc->smmu = NULL; in tegra_mc_probe()
898 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { in tegra_mc_probe()
899 mc->gart = tegra_gart_probe(&pdev->dev, mc); in tegra_mc_probe()
900 if (IS_ERR(mc->gart)) { in tegra_mc_probe()
902 PTR_ERR(mc->gart)); in tegra_mc_probe()
903 mc->gart = NULL; in tegra_mc_probe()
912 struct tegra_mc *mc = dev_get_drvdata(dev); in tegra_mc_suspend() local
914 if (mc->soc->ops && mc->soc->ops->suspend) in tegra_mc_suspend()
915 return mc->soc->ops->suspend(mc); in tegra_mc_suspend()
922 struct tegra_mc *mc = dev_get_drvdata(dev); in tegra_mc_resume() local
924 if (mc->soc->ops && mc->soc->ops->resume) in tegra_mc_resume()
925 return mc->soc->ops->resume(mc); in tegra_mc_resume()
932 struct tegra_mc *mc = dev_get_drvdata(dev); in tegra_mc_sync_state() local
935 if (mc->provider.dev == dev) in tegra_mc_sync_state()
945 .name = "tegra-mc",