124  * @timings_arr_size:	number of 'timings' elements
128  * @timings:		DDR memory timings, from device tree
130  * @bypass_timing_row:	value for timing row register for bypass timings
131  * @bypass_timing_data:	value for timing data register for bypass timings
133  *				timings
169 	const struct lpddr3_timings *timings;  member
301  * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
377  * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
380  * Low-level function for changing timings for DRAM memory clocking from
404  * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
408  * Low-level function for changing timings for DRAM memory operating from main
410  * frequency must have corresponding timings register values in order to keep
498  * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
502  * Function changes the DRAM timings for the temporary 'bypass' mode.
524  * This mode is used only temporary but if required, changes voltage and timings
573  * timings: set 0 and set 1. The set 0 is used when main clock source is
607 	 * We are safe to increase the timings for current bypass frequency.  in exynos5_dmc_change_freq_and_volt()
1031  * The function calculates timings and creates a register value ready for
1032  * a frequency transition. The register contains a few timings. They are
1050 	val = dmc->timings->tRFC / clk_period_ps;  in create_timings_aligned()
1051 	val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1056 	val = dmc->timings->tRRD / clk_period_ps;  in create_timings_aligned()
1057 	val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1062 	val = dmc->timings->tRPab / clk_period_ps;  in create_timings_aligned()
1063 	val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1068 	val = dmc->timings->tRCD / clk_period_ps;  in create_timings_aligned()
1069 	val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1074 	val = dmc->timings->tRC / clk_period_ps;  in create_timings_aligned()
1075 	val += dmc->timings->tRC % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1080 	val = dmc->timings->tRAS / clk_period_ps;  in create_timings_aligned()
1081 	val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1086 	/* data related timings */  in create_timings_aligned()
1087 	val = dmc->timings->tWTR / clk_period_ps;  in create_timings_aligned()
1088 	val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1093 	val = dmc->timings->tWR / clk_period_ps;  in create_timings_aligned()
1094 	val += dmc->timings->tWR % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1099 	val = dmc->timings->tRTP / clk_period_ps;  in create_timings_aligned()
1100 	val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1105 	val = dmc->timings->tW2W_C2C / clk_period_ps;  in create_timings_aligned()
1106 	val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1111 	val = dmc->timings->tR2R_C2C / clk_period_ps;  in create_timings_aligned()
1112 	val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1117 	val = dmc->timings->tWL / clk_period_ps;  in create_timings_aligned()
1118 	val += dmc->timings->tWL % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1123 	val = dmc->timings->tDQSCK / clk_period_ps;  in create_timings_aligned()
1124 	val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1129 	val = dmc->timings->tRL / clk_period_ps;  in create_timings_aligned()
1130 	val += dmc->timings->tRL % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1135 	/* power related timings */  in create_timings_aligned()
1136 	val = dmc->timings->tFAW / clk_period_ps;  in create_timings_aligned()
1137 	val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1142 	val = dmc->timings->tXSR / clk_period_ps;  in create_timings_aligned()
1143 	val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1148 	val = dmc->timings->tXP / clk_period_ps;  in create_timings_aligned()
1149 	val += dmc->timings->tXP % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1154 	val = dmc->timings->tCKE / clk_period_ps;  in create_timings_aligned()
1155 	val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1160 	val = dmc->timings->tMRD / clk_period_ps;  in create_timings_aligned()
1161 	val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;  in create_timings_aligned()
1209 	dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,  in of_get_dram_timings()
1212 	if (!dmc->timings) {  in of_get_dram_timings()
1213 		dev_warn(dmc->dev, "could not get timings from DT\n");  in of_get_dram_timings()
1237 	/* Take the highest frequency's timings as 'bypass' */  in of_get_dram_timings()
1417  * memory parameters: timings for each operating frequency.
1468 		dev_warn(dev, "couldn't initialize timings settings\n");  in exynos5_dmc_probe()