Lines Matching +full:0 +full:x33000000
29 #define TUNER_MODE_FM_RADIO 0
55 u32 temp = 0; in verve_read_byte()
64 u32 _gpio_direction = 0; in initGPIO()
65 u32 value = 0; in initGPIO()
66 u8 val = 0; in initGPIO()
68 _gpio_direction = _gpio_direction & 0xFC0003FF; in initGPIO()
69 _gpio_direction = _gpio_direction | 0x03FDFC00; in initGPIO()
70 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); in initGPIO()
72 verve_read_byte(dev, 0x07, &val); in initGPIO()
73 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); in initGPIO()
74 verve_write_byte(dev, 0x07, 0xF4); in initGPIO()
75 verve_read_byte(dev, 0x07, &val); in initGPIO()
76 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); in initGPIO()
80 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); in initGPIO()
81 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); in initGPIO()
86 u8 value[4] = { 0, 0, 0, 0 }; in uninitGPIO()
88 cx231xx_capture_start(dev, 0, Vbi); in uninitGPIO()
89 verve_write_byte(dev, 0x07, 0x14); in uninitGPIO()
91 0x68, value, 4); in uninitGPIO()
107 u32 temp = 0; in afe_read_byte()
117 int status = 0; in cx231xx_afe_init_super_block()
118 u8 temp = 0; in cx231xx_afe_init_super_block()
119 u8 afe_power_status = 0; in cx231xx_afe_init_super_block()
120 int i = 0; in cx231xx_afe_init_super_block()
123 temp = (u8) (ref_count & 0xff); in cx231xx_afe_init_super_block()
125 if (status < 0) in cx231xx_afe_init_super_block()
129 if (status < 0) in cx231xx_afe_init_super_block()
132 temp = (u8) ((ref_count & 0x300) >> 8); in cx231xx_afe_init_super_block()
133 temp |= 0x40; in cx231xx_afe_init_super_block()
135 if (status < 0) in cx231xx_afe_init_super_block()
138 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); in cx231xx_afe_init_super_block()
139 if (status < 0) in cx231xx_afe_init_super_block()
143 while (afe_power_status != 0x18) { in cx231xx_afe_init_super_block()
144 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); in cx231xx_afe_init_super_block()
145 if (status < 0) { in cx231xx_afe_init_super_block()
153 afe_power_status &= 0xff; in cx231xx_afe_init_super_block()
154 if (status < 0) { in cx231xx_afe_init_super_block()
170 if (status < 0) in cx231xx_afe_init_super_block()
174 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); in cx231xx_afe_init_super_block()
175 if (status < 0) in cx231xx_afe_init_super_block()
181 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); in cx231xx_afe_init_super_block()
188 int status = 0; in cx231xx_afe_init_channels()
191 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); in cx231xx_afe_init_channels()
192 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); in cx231xx_afe_init_channels()
193 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); in cx231xx_afe_init_channels()
196 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); in cx231xx_afe_init_channels()
199 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); in cx231xx_afe_init_channels()
200 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); in cx231xx_afe_init_channels()
201 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); in cx231xx_afe_init_channels()
204 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); in cx231xx_afe_init_channels()
205 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); in cx231xx_afe_init_channels()
206 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); in cx231xx_afe_init_channels()
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); in cx231xx_afe_init_channels()
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); in cx231xx_afe_init_channels()
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); in cx231xx_afe_init_channels()
215 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); in cx231xx_afe_init_channels()
216 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); in cx231xx_afe_init_channels()
217 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); in cx231xx_afe_init_channels()
219 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ in cx231xx_afe_init_channels()
221 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); in cx231xx_afe_init_channels()
223 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); in cx231xx_afe_init_channels()
225 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); in cx231xx_afe_init_channels()
228 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); in cx231xx_afe_init_channels()
229 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); in cx231xx_afe_init_channels()
230 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); in cx231xx_afe_init_channels()
237 u8 c_value = 0; in cx231xx_afe_setup_AFE_for_baseband()
238 int status = 0; in cx231xx_afe_setup_AFE_for_baseband()
241 c_value &= (~(0x50)); in cx231xx_afe_setup_AFE_for_baseband()
261 int status = 0; in cx231xx_afe_set_input_mux()
262 u8 value = 0; in cx231xx_afe_set_input_mux()
264 if (ch1_setting != 0) { in cx231xx_afe_set_input_mux()
268 value &= 0xff; in cx231xx_afe_set_input_mux()
272 if (ch2_setting != 0) { in cx231xx_afe_set_input_mux()
276 value &= 0xff; in cx231xx_afe_set_input_mux()
282 if (ch3_setting != 0) { in cx231xx_afe_set_input_mux()
286 value &= 0xff; in cx231xx_afe_set_input_mux()
295 int status = 0; in cx231xx_afe_set_mode()
333 u8 afe_power_status = 0; in cx231xx_afe_update_power_control()
334 int status = 0; in cx231xx_afe_update_power_control()
359 if (status < 0) in cx231xx_afe_update_power_control()
364 0x00); in cx231xx_afe_update_power_control()
366 0x00); in cx231xx_afe_update_power_control()
368 0x00); in cx231xx_afe_update_power_control()
371 0x70); in cx231xx_afe_update_power_control()
373 0x70); in cx231xx_afe_update_power_control()
375 0x70); in cx231xx_afe_update_power_control()
392 if (status < 0) in cx231xx_afe_update_power_control()
397 0x00); in cx231xx_afe_update_power_control()
399 0x00); in cx231xx_afe_update_power_control()
401 0x00); in cx231xx_afe_update_power_control()
416 if (status < 0) in cx231xx_afe_update_power_control()
421 0x40); in cx231xx_afe_update_power_control()
423 0x40); in cx231xx_afe_update_power_control()
425 0x00); in cx231xx_afe_update_power_control()
428 0x70); in cx231xx_afe_update_power_control()
430 0x70); in cx231xx_afe_update_power_control()
432 0x70); in cx231xx_afe_update_power_control()
449 if (status < 0) in cx231xx_afe_update_power_control()
454 0x00); in cx231xx_afe_update_power_control()
456 0x00); in cx231xx_afe_update_power_control()
458 0x40); in cx231xx_afe_update_power_control()
470 u8 input_mode = 0; in cx231xx_afe_adjust_ref_count()
471 u8 ntf_mode = 0; in cx231xx_afe_adjust_ref_count()
472 int status = 0; in cx231xx_afe_adjust_ref_count()
486 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); in cx231xx_afe_adjust_ref_count()
490 dev->afe_ref_count = 0x23C; in cx231xx_afe_adjust_ref_count()
493 dev->afe_ref_count = 0x24C; in cx231xx_afe_adjust_ref_count()
496 dev->afe_ref_count = 0x258; in cx231xx_afe_adjust_ref_count()
499 dev->afe_ref_count = 0x260; in cx231xx_afe_adjust_ref_count()
522 u32 temp = 0; in vid_blk_read_byte()
543 u8 temp = 0; in cx231xx_check_fw()
544 int status = 0; in cx231xx_check_fw()
546 if (status < 0) in cx231xx_check_fw()
555 int status = 0; in cx231xx_set_video_input_mux()
565 if (status < 0) { in cx231xx_set_video_input_mux()
583 if (status < 0) { in cx231xx_set_video_input_mux()
628 int status = 0; in cx231xx_set_decoder_video_input()
629 u32 value = 0; in cx231xx_set_decoder_video_input()
633 if (status < 0) { in cx231xx_set_decoder_video_input()
643 if (status < 0) { in cx231xx_set_decoder_video_input()
653 value |= (0 << 13) | (1 << 4); in cx231xx_set_decoder_video_input()
656 /* set [24:23] [22:15] to 0 */ in cx231xx_set_decoder_video_input()
657 value &= (~(0x1ff8000)); in cx231xx_set_decoder_video_input()
658 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ in cx231xx_set_decoder_video_input()
659 value |= 0x1000000; in cx231xx_set_decoder_video_input()
675 if (status < 0) { in cx231xx_set_decoder_video_input()
711 /* set [24:23] [22:15] to 0 */ in cx231xx_set_decoder_video_input()
712 value &= (~(0x1ff8000)); in cx231xx_set_decoder_video_input()
714 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ in cx231xx_set_decoder_video_input()
715 value |= 0x1000010; in cx231xx_set_decoder_video_input()
720 if (status < 0) { in cx231xx_set_decoder_video_input()
773 value |= (0 << 13) | (1 << 4); in cx231xx_set_decoder_video_input()
776 /* set [24:23] [22:15] to 0 */ in cx231xx_set_decoder_video_input()
777 value &= (~(0x1FF8000)); in cx231xx_set_decoder_video_input()
778 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ in cx231xx_set_decoder_video_input()
779 value |= 0x1000000; in cx231xx_set_decoder_video_input()
795 if (status < 0) { in cx231xx_set_decoder_video_input()
831 if (status < 0) { in cx231xx_set_decoder_video_input()
855 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; in cx231xx_set_decoder_video_input()
904 value |= 0x800000; in cx231xx_set_decoder_video_input()
914 (value & 0xFFFFFFEF)); in cx231xx_set_decoder_video_input()
930 if (value & 0x02) { in cx231xx_set_decoder_video_input()
940 u8 temp = 0; in cx231xx_enable656()
941 /*enable TS1 data[0:7] as output to export 656*/ in cx231xx_enable656()
943 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); in cx231xx_enable656()
948 temp = temp|0x04; in cx231xx_enable656()
956 u8 temp = 0; in cx231xx_disable656()
958 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); in cx231xx_disable656()
961 temp = temp&0xFB; in cx231xx_disable656()
974 int status = 0; in cx231xx_do_mode_ctrl_overrides()
976 dev_dbg(dev->dev, "%s: 0x%x\n", in cx231xx_do_mode_ctrl_overrides()
980 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); in cx231xx_do_mode_ctrl_overrides()
990 FLD_VBLANK_CNT, 0x18); in cx231xx_do_mode_ctrl_overrides()
995 0x1E7000); in cx231xx_do_mode_ctrl_overrides()
1000 0x1C000000); in cx231xx_do_mode_ctrl_overrides()
1007 (FLD_HBLANK_CNT, 0x79)); in cx231xx_do_mode_ctrl_overrides()
1014 FLD_VBLANK_CNT, 0x20); in cx231xx_do_mode_ctrl_overrides()
1021 0x244)); in cx231xx_do_mode_ctrl_overrides()
1028 0x24)); in cx231xx_do_mode_ctrl_overrides()
1035 (FLD_HBLANK_CNT, 0x85)); in cx231xx_do_mode_ctrl_overrides()
1041 FLD_VBLANK_CNT, 0x20); in cx231xx_do_mode_ctrl_overrides()
1048 0x244)); in cx231xx_do_mode_ctrl_overrides()
1055 0x24)); in cx231xx_do_mode_ctrl_overrides()
1062 (FLD_HBLANK_CNT, 0x85)); in cx231xx_do_mode_ctrl_overrides()
1071 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); in cx231xx_unmute_audio()
1077 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); in stopAudioFirmware()
1082 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); in restartAudioFirmware()
1087 int status = 0; in cx231xx_set_audio_input()
1113 u32 value = 0; in cx231xx_set_audio_decoder_input()
1137 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | in cx231xx_set_audio_decoder_input()
1138 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | in cx231xx_set_audio_decoder_input()
1139 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); in cx231xx_set_audio_decoder_input()
1142 adr 08d0, data 0x00063073 */ in cx231xx_set_audio_decoder_input()
1143 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); in cx231xx_set_audio_decoder_input()
1144 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); in cx231xx_set_audio_decoder_input()
1162 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | in cx231xx_set_audio_decoder_input()
1163 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | in cx231xx_set_audio_decoder_input()
1164 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | in cx231xx_set_audio_decoder_input()
1165 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | in cx231xx_set_audio_decoder_input()
1166 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | in cx231xx_set_audio_decoder_input()
1167 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | in cx231xx_set_audio_decoder_input()
1168 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | in cx231xx_set_audio_decoder_input()
1169 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | in cx231xx_set_audio_decoder_input()
1170 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | in cx231xx_set_audio_decoder_input()
1171 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | in cx231xx_set_audio_decoder_input()
1172 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | in cx231xx_set_audio_decoder_input()
1173 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | in cx231xx_set_audio_decoder_input()
1174 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); in cx231xx_set_audio_decoder_input()
1178 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | in cx231xx_set_audio_decoder_input()
1179 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | in cx231xx_set_audio_decoder_input()
1180 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | in cx231xx_set_audio_decoder_input()
1181 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | in cx231xx_set_audio_decoder_input()
1182 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); in cx231xx_set_audio_decoder_input()
1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); in cx231xx_set_audio_decoder_input()
1187 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); in cx231xx_set_audio_decoder_input()
1206 cx231xx_set_field(FLD_SIF_EN, 0)); in cx231xx_set_audio_decoder_input()
1236 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); in cx231xx_set_audio_decoder_input()
1254 int status = 0; in cx231xx_init_ctrl_pin_status()
1273 /* 0 - demod ; 1 - Analog mode */ in cx231xx_set_agc_analog_digital_mux_select()
1278 if (status < 0) in cx231xx_set_agc_analog_digital_mux_select()
1281 return 0; in cx231xx_set_agc_analog_digital_mux_select()
1286 u8 value[4] = { 0, 0, 0, 0 }; in cx231xx_enable_i2c_port_3()
1287 int status = 0; in cx231xx_enable_i2c_port_3()
1299 if (status < 0) in cx231xx_enable_i2c_port_3()
1302 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; in cx231xx_enable_i2c_port_3()
1306 return 0; in cx231xx_enable_i2c_port_3()
1309 value[0] |= I2C_DEMOD_EN; in cx231xx_enable_i2c_port_3()
1311 value[0] &= ~I2C_DEMOD_EN; in cx231xx_enable_i2c_port_3()
1317 if (status >= 0) in cx231xx_enable_i2c_port_3()
1328 u8 status = 0; in update_HH_register_after_set_DIF()
1329 u32 value = 0; in update_HH_register_after_set_DIF()
1331 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); in update_HH_register_after_set_DIF()
1332 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); in update_HH_register_after_set_DIF()
1333 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); in update_HH_register_after_set_DIF()
1336 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); in update_HH_register_after_set_DIF()
1343 u32 value = 0; in cx231xx_dump_HH_reg()
1344 u16 i = 0; in cx231xx_dump_HH_reg()
1346 value = 0x45005390; in cx231xx_dump_HH_reg()
1347 vid_blk_write_word(dev, 0x104, value); in cx231xx_dump_HH_reg()
1349 for (i = 0x100; i < 0x140; i++) { in cx231xx_dump_HH_reg()
1351 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); in cx231xx_dump_HH_reg()
1355 for (i = 0x300; i < 0x400; i++) { in cx231xx_dump_HH_reg()
1357 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); in cx231xx_dump_HH_reg()
1361 for (i = 0x400; i < 0x440; i++) { in cx231xx_dump_HH_reg()
1363 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); in cx231xx_dump_HH_reg()
1368 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); in cx231xx_dump_HH_reg()
1369 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); in cx231xx_dump_HH_reg()
1371 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); in cx231xx_dump_HH_reg()
1374 #if 0
1377 u8 value[4] = { 0, 0, 0, 0 };
1383 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1388 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1393 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1398 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1404 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1409 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1414 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1419 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1425 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1430 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1435 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1440 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1446 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1451 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1456 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1461 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1467 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1472 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1480 u8 value = 0; in cx231xx_Setup_AFE_for_LowIF()
1483 value = (value & 0xFE)|0x01; in cx231xx_Setup_AFE_for_LowIF()
1487 value = (value & 0xFE)|0x00; in cx231xx_Setup_AFE_for_LowIF()
1494 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce in cx231xx_Setup_AFE_for_LowIF()
1501 value = (value & 0xFC)|0x00; in cx231xx_Setup_AFE_for_LowIF()
1505 value = (value & 0xF9)|0x02; in cx231xx_Setup_AFE_for_LowIF()
1509 value = (value & 0xFB)|0x04; in cx231xx_Setup_AFE_for_LowIF()
1513 value = (value & 0xFC)|0x03; in cx231xx_Setup_AFE_for_LowIF()
1517 value = (value & 0xFB)|0x04; in cx231xx_Setup_AFE_for_LowIF()
1521 value = (value & 0xF8)|0x06; in cx231xx_Setup_AFE_for_LowIF()
1525 value = (value & 0x8F)|0x40; in cx231xx_Setup_AFE_for_LowIF()
1529 value = (value & 0xDF)|0x20; in cx231xx_Setup_AFE_for_LowIF()
1536 u32 colibri_carrier_offset = 0; in cx231xx_set_Colibri_For_LowIF()
1537 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ in cx231xx_set_Colibri_For_LowIF()
1538 u32 standard = 0; in cx231xx_set_Colibri_For_LowIF()
1539 u8 value[4] = { 0, 0, 0, 0 }; in cx231xx_set_Colibri_For_LowIF()
1542 value[0] = (u8) 0x6F; in cx231xx_set_Colibri_For_LowIF()
1543 value[1] = (u8) 0x6F; in cx231xx_set_Colibri_For_LowIF()
1544 value[2] = (u8) 0x6F; in cx231xx_set_Colibri_For_LowIF()
1545 value[3] = (u8) 0x6F; in cx231xx_set_Colibri_For_LowIF()
1561 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n", in cx231xx_set_Colibri_For_LowIF()
1571 u32 colibri_carrier_offset = 0; in cx231xx_Get_Colibri_CarrierOffset()
1591 u32 dif_misc_ctrl_value = 0; in cx231xx_set_DIF_bandpass()
1592 u64 pll_freq_u64 = 0; in cx231xx_set_DIF_bandpass()
1593 u32 i = 0; in cx231xx_set_DIF_bandpass()
1595 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", in cx231xx_set_DIF_bandpass()
1600 pll_freq_word = 0x905A1CAC; in cx231xx_set_DIF_bandpass()
1609 /*pll_freq_word = 0x3463497;*/ in cx231xx_set_DIF_bandpass()
1617 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; in cx231xx_set_DIF_bandpass()
1625 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; in cx231xx_set_DIF_bandpass()
1640 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { in cx231xx_set_DIF_bandpass()
1654 int status = 0; in cx231xx_dif_configure_C2HH_for_low_IF()
1662 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1670 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); in cx231xx_dif_configure_C2HH_for_low_IF()
1674 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1680 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1689 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); in cx231xx_dif_configure_C2HH_for_low_IF()
1693 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1694 /* 0x124, AUD_CHAN1_SRC = 0x3 */ in cx231xx_dif_configure_C2HH_for_low_IF()
1697 AUD_IO_CTRL, 0, 31, 0x00000003); in cx231xx_dif_configure_C2HH_for_low_IF()
1705 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1714 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); in cx231xx_dif_configure_C2HH_for_low_IF()
1718 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1725 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1734 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); in cx231xx_dif_configure_C2HH_for_low_IF()
1738 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); in cx231xx_dif_configure_C2HH_for_low_IF()
1747 int status = 0; in cx231xx_dif_set_standard()
1748 u32 dif_misc_ctrl_value = 0; in cx231xx_dif_set_standard()
1749 u32 func_mode = 0; in cx231xx_dif_set_standard()
1765 func_mode = 0x03; in cx231xx_dif_set_standard()
1771 func_mode = 0x01; in cx231xx_dif_set_standard()
1774 func_mode = 0x01; in cx231xx_dif_set_standard()
1783 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); in cx231xx_dif_set_standard()
1791 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); in cx231xx_dif_set_standard()
1793 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); in cx231xx_dif_set_standard()
1795 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); in cx231xx_dif_set_standard()
1797 DIF_PLL_CTRL3, 0, 31, 0x00008800); in cx231xx_dif_set_standard()
1799 DIF_AGC_IF_REF, 0, 31, 0x444C1380); in cx231xx_dif_set_standard()
1801 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); in cx231xx_dif_set_standard()
1803 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); in cx231xx_dif_set_standard()
1805 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); in cx231xx_dif_set_standard()
1807 DIF_AGC_IF_INT_CURRENT, 0, 31, in cx231xx_dif_set_standard()
1808 0x26001700); in cx231xx_dif_set_standard()
1810 DIF_AGC_RF_CURRENT, 0, 31, in cx231xx_dif_set_standard()
1811 0x00002660); in cx231xx_dif_set_standard()
1813 DIF_VIDEO_AGC_CTRL, 0, 31, in cx231xx_dif_set_standard()
1814 0x72500800); in cx231xx_dif_set_standard()
1816 DIF_VID_AUD_OVERRIDE, 0, 31, in cx231xx_dif_set_standard()
1817 0x27000100); in cx231xx_dif_set_standard()
1819 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); in cx231xx_dif_set_standard()
1821 DIF_COMP_FLT_CTRL, 0, 31, in cx231xx_dif_set_standard()
1822 0x00000000); in cx231xx_dif_set_standard()
1824 DIF_SRC_PHASE_INC, 0, 31, in cx231xx_dif_set_standard()
1825 0x1befbf06); in cx231xx_dif_set_standard()
1827 DIF_SRC_GAIN_CONTROL, 0, 31, in cx231xx_dif_set_standard()
1828 0x000035e8); in cx231xx_dif_set_standard()
1830 DIF_RPT_VARIANCE, 0, 31, 0x00000000); in cx231xx_dif_set_standard()
1833 dif_misc_ctrl_value |= 0x3a023F11; in cx231xx_dif_set_standard()
1836 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); in cx231xx_dif_set_standard()
1838 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); in cx231xx_dif_set_standard()
1840 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); in cx231xx_dif_set_standard()
1842 DIF_PLL_CTRL3, 0, 31, 0x00008800); in cx231xx_dif_set_standard()
1844 DIF_AGC_IF_REF, 0, 31, 0x444C1380); in cx231xx_dif_set_standard()
1846 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); in cx231xx_dif_set_standard()
1848 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); in cx231xx_dif_set_standard()
1850 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); in cx231xx_dif_set_standard()
1852 DIF_AGC_IF_INT_CURRENT, 0, 31, in cx231xx_dif_set_standard()
1853 0x26001700); in cx231xx_dif_set_standard()
1855 DIF_AGC_RF_CURRENT, 0, 31, in cx231xx_dif_set_standard()
1856 0x00002660); in cx231xx_dif_set_standard()
1858 DIF_VIDEO_AGC_CTRL, 0, 31, in cx231xx_dif_set_standard()
1859 0x72500800); in cx231xx_dif_set_standard()
1861 DIF_VID_AUD_OVERRIDE, 0, 31, in cx231xx_dif_set_standard()
1862 0x27000100); in cx231xx_dif_set_standard()
1864 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); in cx231xx_dif_set_standard()
1866 DIF_COMP_FLT_CTRL, 0, 31, in cx231xx_dif_set_standard()
1867 0x00000000); in cx231xx_dif_set_standard()
1869 DIF_SRC_PHASE_INC, 0, 31, in cx231xx_dif_set_standard()
1870 0x1befbf06); in cx231xx_dif_set_standard()
1872 DIF_SRC_GAIN_CONTROL, 0, 31, in cx231xx_dif_set_standard()
1873 0x000035e8); in cx231xx_dif_set_standard()
1875 DIF_RPT_VARIANCE, 0, 31, 0x00000000); in cx231xx_dif_set_standard()
1878 dif_misc_ctrl_value |= 0x3a033F11; in cx231xx_dif_set_standard()
1881 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); in cx231xx_dif_set_standard()
1882 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); in cx231xx_dif_set_standard()
1883 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); in cx231xx_dif_set_standard()
1884 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); in cx231xx_dif_set_standard()
1885 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); in cx231xx_dif_set_standard()
1887 0x26001700); in cx231xx_dif_set_standard()
1889 0x00002660); in cx231xx_dif_set_standard()
1891 0x72500800); in cx231xx_dif_set_standard()
1893 0x27000100); in cx231xx_dif_set_standard()
1894 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); in cx231xx_dif_set_standard()
1896 0x009f50c1); in cx231xx_dif_set_standard()
1898 0x1befbf06); in cx231xx_dif_set_standard()
1900 0x000035e8); in cx231xx_dif_set_standard()
1902 0x00000000); in cx231xx_dif_set_standard()
1905 dif_misc_ctrl_value |= 0x3A0A3F10; in cx231xx_dif_set_standard()
1908 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); in cx231xx_dif_set_standard()
1909 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); in cx231xx_dif_set_standard()
1910 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); in cx231xx_dif_set_standard()
1911 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); in cx231xx_dif_set_standard()
1912 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); in cx231xx_dif_set_standard()
1914 0x26001700); in cx231xx_dif_set_standard()
1916 0x00002660); in cx231xx_dif_set_standard()
1918 0x72500800); in cx231xx_dif_set_standard()
1920 0x27000100); in cx231xx_dif_set_standard()
1922 0x012c405d); in cx231xx_dif_set_standard()
1924 0x009f50c1); in cx231xx_dif_set_standard()
1926 0x1befbf06); in cx231xx_dif_set_standard()
1928 0x000035e8); in cx231xx_dif_set_standard()
1930 0x00000000); in cx231xx_dif_set_standard()
1933 dif_misc_ctrl_value = 0x3A093F10; in cx231xx_dif_set_standard()
1939 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); in cx231xx_dif_set_standard()
1941 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); in cx231xx_dif_set_standard()
1943 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); in cx231xx_dif_set_standard()
1945 DIF_PLL_CTRL3, 0, 31, 0x00008800); in cx231xx_dif_set_standard()
1947 DIF_AGC_IF_REF, 0, 31, 0x888C0380); in cx231xx_dif_set_standard()
1949 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); in cx231xx_dif_set_standard()
1951 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); in cx231xx_dif_set_standard()
1953 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); in cx231xx_dif_set_standard()
1955 DIF_AGC_IF_INT_CURRENT, 0, 31, in cx231xx_dif_set_standard()
1956 0x26001700); in cx231xx_dif_set_standard()
1958 DIF_AGC_RF_CURRENT, 0, 31, in cx231xx_dif_set_standard()
1959 0x00002660); in cx231xx_dif_set_standard()
1961 DIF_VID_AUD_OVERRIDE, 0, 31, in cx231xx_dif_set_standard()
1962 0x27000100); in cx231xx_dif_set_standard()
1964 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); in cx231xx_dif_set_standard()
1966 DIF_COMP_FLT_CTRL, 0, 31, in cx231xx_dif_set_standard()
1967 0x00000000); in cx231xx_dif_set_standard()
1969 DIF_SRC_PHASE_INC, 0, 31, in cx231xx_dif_set_standard()
1970 0x1befbf06); in cx231xx_dif_set_standard()
1972 DIF_SRC_GAIN_CONTROL, 0, 31, in cx231xx_dif_set_standard()
1973 0x000035e8); in cx231xx_dif_set_standard()
1975 DIF_RPT_VARIANCE, 0, 31, 0x00000000); in cx231xx_dif_set_standard()
1977 DIF_VIDEO_AGC_CTRL, 0, 31, in cx231xx_dif_set_standard()
1978 0xf4000000); in cx231xx_dif_set_standard()
1982 dif_misc_ctrl_value |= 0x3a023F11; in cx231xx_dif_set_standard()
1986 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); in cx231xx_dif_set_standard()
1988 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); in cx231xx_dif_set_standard()
1990 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); in cx231xx_dif_set_standard()
1992 DIF_PLL_CTRL3, 0, 31, 0x00008800); in cx231xx_dif_set_standard()
1994 DIF_AGC_IF_REF, 0, 31, 0x888C0380); in cx231xx_dif_set_standard()
1996 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); in cx231xx_dif_set_standard()
1998 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); in cx231xx_dif_set_standard()
2000 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); in cx231xx_dif_set_standard()
2002 DIF_AGC_IF_INT_CURRENT, 0, 31, in cx231xx_dif_set_standard()
2003 0x26001700); in cx231xx_dif_set_standard()
2005 DIF_AGC_RF_CURRENT, 0, 31, in cx231xx_dif_set_standard()
2006 0x00002660); in cx231xx_dif_set_standard()
2008 DIF_VID_AUD_OVERRIDE, 0, 31, in cx231xx_dif_set_standard()
2009 0x27000100); in cx231xx_dif_set_standard()
2011 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); in cx231xx_dif_set_standard()
2013 DIF_COMP_FLT_CTRL, 0, 31, in cx231xx_dif_set_standard()
2014 0x00000000); in cx231xx_dif_set_standard()
2016 DIF_SRC_PHASE_INC, 0, 31, in cx231xx_dif_set_standard()
2017 0x1befbf06); in cx231xx_dif_set_standard()
2019 DIF_SRC_GAIN_CONTROL, 0, 31, in cx231xx_dif_set_standard()
2020 0x000035e8); in cx231xx_dif_set_standard()
2022 DIF_RPT_VARIANCE, 0, 31, 0x00000000); in cx231xx_dif_set_standard()
2024 DIF_VIDEO_AGC_CTRL, 0, 31, in cx231xx_dif_set_standard()
2025 0xf2560000); in cx231xx_dif_set_standard()
2029 dif_misc_ctrl_value |= 0x3a023F11; in cx231xx_dif_set_standard()
2033 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ in cx231xx_dif_set_standard()
2038 the pll freq word is 0x03420c49 in cx231xx_dif_set_standard()
2041 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); in cx231xx_dif_set_standard()
2042 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); in cx231xx_dif_set_standard()
2043 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); in cx231xx_dif_set_standard()
2044 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); in cx231xx_dif_set_standard()
2045 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); in cx231xx_dif_set_standard()
2047 0x26001700); in cx231xx_dif_set_standard()
2049 0x00002660); in cx231xx_dif_set_standard()
2051 0x04000800); in cx231xx_dif_set_standard()
2053 0x27000100); in cx231xx_dif_set_standard()
2054 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); in cx231xx_dif_set_standard()
2057 0x009f50c1); in cx231xx_dif_set_standard()
2059 0x1befbf06); in cx231xx_dif_set_standard()
2061 0x000035e8); in cx231xx_dif_set_standard()
2063 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); in cx231xx_dif_set_standard()
2065 0xC2262600); in cx231xx_dif_set_standard()
2066 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); in cx231xx_dif_set_standard()
2070 dif_misc_ctrl_value |= 0x3a003F10; in cx231xx_dif_set_standard()
2074 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); in cx231xx_dif_set_standard()
2076 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); in cx231xx_dif_set_standard()
2078 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); in cx231xx_dif_set_standard()
2080 DIF_PLL_CTRL3, 0, 31, 0x00008800); in cx231xx_dif_set_standard()
2082 DIF_AGC_IF_REF, 0, 31, 0x444C1380); in cx231xx_dif_set_standard()
2084 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); in cx231xx_dif_set_standard()
2086 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); in cx231xx_dif_set_standard()
2088 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); in cx231xx_dif_set_standard()
2090 DIF_AGC_IF_INT_CURRENT, 0, 31, in cx231xx_dif_set_standard()
2091 0x26001700); in cx231xx_dif_set_standard()
2093 DIF_AGC_RF_CURRENT, 0, 31, in cx231xx_dif_set_standard()
2094 0x00002660); in cx231xx_dif_set_standard()
2096 DIF_VIDEO_AGC_CTRL, 0, 31, in cx231xx_dif_set_standard()
2097 0x72500800); in cx231xx_dif_set_standard()
2099 DIF_VID_AUD_OVERRIDE, 0, 31, in cx231xx_dif_set_standard()
2100 0x27000100); in cx231xx_dif_set_standard()
2102 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); in cx231xx_dif_set_standard()
2104 DIF_COMP_FLT_CTRL, 0, 31, in cx231xx_dif_set_standard()
2105 0x00A653A8); in cx231xx_dif_set_standard()
2107 DIF_SRC_PHASE_INC, 0, 31, in cx231xx_dif_set_standard()
2108 0x1befbf06); in cx231xx_dif_set_standard()
2110 DIF_SRC_GAIN_CONTROL, 0, 31, in cx231xx_dif_set_standard()
2111 0x000035e8); in cx231xx_dif_set_standard()
2113 DIF_RPT_VARIANCE, 0, 31, 0x00000000); in cx231xx_dif_set_standard()
2116 dif_misc_ctrl_value |= 0x3a013F11; in cx231xx_dif_set_standard()
2127 dif_misc_ctrl_value = 0x7a080000; in cx231xx_dif_set_standard()
2137 int status = 0; in cx231xx_tuner_pre_channel_change()
2143 dwval |= 0x33000000; in cx231xx_tuner_pre_channel_change()
2152 int status = 0; in cx231xx_tuner_post_channel_change()
2154 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n", in cx231xx_tuner_post_channel_change()
2165 dwval |= 0x88000300; in cx231xx_tuner_post_channel_change()
2167 dwval |= 0x88000000; in cx231xx_tuner_post_channel_change()
2171 dwval |= 0xCC000300; in cx231xx_tuner_post_channel_change()
2173 dwval |= 0x44000000; in cx231xx_tuner_post_channel_change()
2178 return status == sizeof(dwval) ? 0 : -EIO; in cx231xx_tuner_post_channel_change()
2186 int status = 0; in cx231xx_i2s_blk_initialize()
2192 value |= 0x80; in cx231xx_i2s_blk_initialize()
2197 CH_PWR_CTRL2, 1, 0x00, 1); in cx231xx_i2s_blk_initialize()
2205 int status = 0; in cx231xx_i2s_blk_update_power_control()
2206 u32 value = 0; in cx231xx_i2s_blk_update_power_control()
2211 value |= 0xfe; in cx231xx_i2s_blk_update_power_control()
2216 CH_PWR_CTRL2, 1, 0x00, 1); in cx231xx_i2s_blk_update_power_control()
2225 int status = 0; in cx231xx_i2s_blk_set_audio_input()
2230 CH_PWR_CTRL2, 1, 0x00, 1); in cx231xx_i2s_blk_set_audio_input()
2232 CH_PWR_CTRL1, 1, 0x80, 1); in cx231xx_i2s_blk_set_audio_input()
2249 u8 value[4] = { 0, 0, 0, 0 }; in cx231xx_set_power_mode()
2250 u32 tmp = 0; in cx231xx_set_power_mode()
2251 int status = 0; in cx231xx_set_power_mode()
2258 return 0; in cx231xx_set_power_mode()
2263 if (status < 0) in cx231xx_set_power_mode()
2274 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2283 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2293 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2301 dev->xc_fw_load_done = 0; in cx231xx_set_power_mode()
2307 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2317 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2328 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2338 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2349 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2372 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2382 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2392 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2403 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2413 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2442 value[0] = (u8) tmp; in cx231xx_set_power_mode()
2465 u8 value[4] = { 0, 0, 0, 0 }; in cx231xx_power_suspend()
2466 u32 tmp = 0; in cx231xx_power_suspend()
2467 int status = 0; in cx231xx_power_suspend()
2471 if (status > 0) in cx231xx_power_suspend()
2477 value[0] = (u8) tmp; in cx231xx_power_suspend()
2492 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; in cx231xx_start_stream()
2493 u32 tmp = 0; in cx231xx_start_stream()
2494 int status = 0; in cx231xx_start_stream()
2499 if (status < 0) in cx231xx_start_stream()
2504 value[0] = (u8) tmp; in cx231xx_start_stream()
2517 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; in cx231xx_stop_stream()
2518 u32 tmp = 0; in cx231xx_stop_stream()
2519 int status = 0; in cx231xx_stop_stream()
2524 if (status < 0) in cx231xx_stop_stream()
2529 value[0] = (u8) tmp; in cx231xx_stop_stream()
2542 int status = 0; in cx231xx_initialize_stream_xfer()
2543 u32 value = 0; in cx231xx_initialize_stream_xfer()
2544 u8 val[4] = { 0, 0, 0, 0 }; in cx231xx_initialize_stream_xfer()
2552 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); in cx231xx_initialize_stream_xfer()
2558 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); in cx231xx_initialize_stream_xfer()
2565 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); in cx231xx_initialize_stream_xfer()
2571 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); in cx231xx_initialize_stream_xfer()
2581 value &= 0xFFFFFFFC; in cx231xx_initialize_stream_xfer()
2582 value |= 0x3; in cx231xx_initialize_stream_xfer()
2587 val[0] = 0x04; in cx231xx_initialize_stream_xfer()
2588 val[1] = 0xA3; in cx231xx_initialize_stream_xfer()
2589 val[2] = 0x3B; in cx231xx_initialize_stream_xfer()
2590 val[3] = 0x00; in cx231xx_initialize_stream_xfer()
2595 val[0] = 0x00; in cx231xx_initialize_stream_xfer()
2596 val[1] = 0x08; in cx231xx_initialize_stream_xfer()
2597 val[2] = 0x00; in cx231xx_initialize_stream_xfer()
2598 val[3] = 0x08; in cx231xx_initialize_stream_xfer()
2605 TS_MODE_REG, 0x101); in cx231xx_initialize_stream_xfer()
2607 TS1_CFG_REG, 0x010); in cx231xx_initialize_stream_xfer()
2615 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); in cx231xx_initialize_stream_xfer()
2616 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); in cx231xx_initialize_stream_xfer()
2620 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); in cx231xx_initialize_stream_xfer()
2662 if (rc < 0) in cx231xx_capture_start()
2666 if (ep_mask > 0) in cx231xx_capture_start()
2670 if (ep_mask > 0) in cx231xx_capture_start()
2683 int status = 0; in cx231xx_set_gpio_bit()
2686 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); in cx231xx_set_gpio_bit()
2694 int status = 0; in cx231xx_get_gpio_bit()
2696 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); in cx231xx_get_gpio_bit()
2708 * from 0 to 31
2710 * 0 = Input direction
2716 int status = 0; in cx231xx_set_gpio_direction()
2717 u32 value = 0; in cx231xx_set_gpio_direction()
2724 if (pin_value == 0) in cx231xx_set_gpio_direction()
2745 * 0 = set it to 0
2750 int status = 0; in cx231xx_set_gpio_value()
2751 u32 value = 0; in cx231xx_set_gpio_value()
2753 /* Check for valid pin_number - if 0xFF , bail out */ in cx231xx_set_gpio_value()
2758 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { in cx231xx_set_gpio_value()
2764 value = 0; in cx231xx_set_gpio_value()
2767 if (pin_value == 0) in cx231xx_set_gpio_value()
2786 int status = 0; in cx231xx_gpio_i2c_start()
2795 if (status < 0) in cx231xx_gpio_i2c_start()
2798 /* set SCL to output 1; set SDA to output 0 */ in cx231xx_gpio_i2c_start()
2803 if (status < 0) in cx231xx_gpio_i2c_start()
2806 /* set SCL to output 0; set SDA to output 0 */ in cx231xx_gpio_i2c_start()
2811 if (status < 0) in cx231xx_gpio_i2c_start()
2819 int status = 0; in cx231xx_gpio_i2c_end()
2821 /* set SCL to output 0; set SDA to output 0 */ in cx231xx_gpio_i2c_end()
2829 if (status < 0) in cx231xx_gpio_i2c_end()
2832 /* set SCL to output 1; set SDA to output 0 */ in cx231xx_gpio_i2c_end()
2837 if (status < 0) in cx231xx_gpio_i2c_end()
2847 if (status < 0) in cx231xx_gpio_i2c_end()
2855 int status = 0; in cx231xx_gpio_i2c_write_byte()
2862 for (i = 0; i < 8; i++) { in cx231xx_gpio_i2c_write_byte()
2863 if (((data << i) & 0x80) == 0) { in cx231xx_gpio_i2c_write_byte()
2864 /* set SCL to output 0; set SDA to output 0 */ in cx231xx_gpio_i2c_write_byte()
2870 /* set SCL to output 1; set SDA to output 0 */ in cx231xx_gpio_i2c_write_byte()
2875 /* set SCL to output 0; set SDA to output 0 */ in cx231xx_gpio_i2c_write_byte()
2880 /* set SCL to output 0; set SDA to output 1 */ in cx231xx_gpio_i2c_write_byte()
2891 /* set SCL to output 0; set SDA to output 1 */ in cx231xx_gpio_i2c_write_byte()
2902 u8 value = 0; in cx231xx_gpio_i2c_read_byte()
2903 int status = 0; in cx231xx_gpio_i2c_read_byte()
2904 u32 gpio_logic_value = 0; in cx231xx_gpio_i2c_read_byte()
2908 for (i = 0; i < 8; i++) { /* send write I2c addr */ in cx231xx_gpio_i2c_read_byte()
2910 /* set SCL to output 0; set SDA to input */ in cx231xx_gpio_i2c_read_byte()
2924 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) in cx231xx_gpio_i2c_read_byte()
2930 /* set SCL to output 0,finish the read latest SCL signal. in cx231xx_gpio_i2c_read_byte()
2937 *buf = value & 0xff; in cx231xx_gpio_i2c_read_byte()
2944 int status = 0; in cx231xx_gpio_i2c_read_ack()
2945 u32 gpio_logic_value = 0; in cx231xx_gpio_i2c_read_ack()
2963 (1 << dev->board.tuner_scl_gpio)) == 0) && in cx231xx_gpio_i2c_read_ack()
2964 (nCnt > 0)); in cx231xx_gpio_i2c_read_ack()
2966 if (nCnt == 0) in cx231xx_gpio_i2c_read_ack()
2978 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { in cx231xx_gpio_i2c_read_ack()
2981 status = 0; in cx231xx_gpio_i2c_read_ack()
2987 /* read SDA end, set the SCL to output 0, after this operation, in cx231xx_gpio_i2c_read_ack()
2999 int status = 0; in cx231xx_gpio_i2c_write_ack()
3005 /* set SCL = 0 (output); set SDA = 0 (output) */ in cx231xx_gpio_i2c_write_ack()
3010 /* set SCL = 1 (output); set SDA = 0 (output) */ in cx231xx_gpio_i2c_write_ack()
3014 /* set SCL = 0 (output); set SDA = 0 (output) */ in cx231xx_gpio_i2c_write_ack()
3027 int status = 0; in cx231xx_gpio_i2c_write_nak()
3034 /* set scl to output 0; set sda to input */ in cx231xx_gpio_i2c_write_nak()
3053 int status = 0; in cx231xx_gpio_i2c_read()
3054 int i = 0; in cx231xx_gpio_i2c_read()
3069 for (i = 0; i < len; i++) { in cx231xx_gpio_i2c_read()
3071 buf[i] = 0; in cx231xx_gpio_i2c_read()
3097 int i = 0; in cx231xx_gpio_i2c_write()
3111 for (i = 0; i < len; i++) { in cx231xx_gpio_i2c_write()
3125 return 0; in cx231xx_gpio_i2c_write()