Lines Matching +full:0 +full:x1d
17 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
24 return 0; in fc0013_writereg()
30 { .addr = priv->addr, .flags = 0, .buf = ®, .len = 1 }, in fc0013_readreg()
38 return 0; in fc0013_readreg()
50 int i, ret = 0; in fc0013_init()
52 0x00, /* reg. 0x00: dummy */ in fc0013_init()
53 0x09, /* reg. 0x01 */ in fc0013_init()
54 0x16, /* reg. 0x02 */ in fc0013_init()
55 0x00, /* reg. 0x03 */ in fc0013_init()
56 0x00, /* reg. 0x04 */ in fc0013_init()
57 0x17, /* reg. 0x05 */ in fc0013_init()
58 0x02, /* reg. 0x06 */ in fc0013_init()
59 0x0a, /* reg. 0x07: CHECK */ in fc0013_init()
60 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, in fc0013_init()
62 0x6f, /* reg. 0x09: enable LoopThrough */ in fc0013_init()
63 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ in fc0013_init()
64 0x82, /* reg. 0x0b: CHECK */ in fc0013_init()
65 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ in fc0013_init()
66 0x01, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */ in fc0013_init()
67 0x00, /* reg. 0x0e */ in fc0013_init()
68 0x00, /* reg. 0x0f */ in fc0013_init()
69 0x00, /* reg. 0x10 */ in fc0013_init()
70 0x00, /* reg. 0x11 */ in fc0013_init()
71 0x00, /* reg. 0x12 */ in fc0013_init()
72 0x00, /* reg. 0x13 */ in fc0013_init()
73 0x50, /* reg. 0x14: DVB-t High Gain, UHF. in fc0013_init()
74 Middle Gain: 0x48, Low Gain: 0x40 */ in fc0013_init()
75 0x01, /* reg. 0x15 */ in fc0013_init()
81 reg[0x07] |= 0x20; in fc0013_init()
89 reg[0x0c] |= 0x02; in fc0013_init()
101 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0013_init()
112 return 0; in fc0013_sleep()
126 ret = fc0013_writereg(priv, 0x10, 0x00); in fc0013_rc_cal_add()
131 ret = fc0013_readreg(priv, 0x10, &rc_cal); in fc0013_rc_cal_add()
135 rc_cal &= 0x0f; in fc0013_rc_cal_add()
140 ret = fc0013_writereg(priv, 0x0d, 0x11); in fc0013_rc_cal_add()
146 ret = fc0013_writereg(priv, 0x10, 0x0f); in fc0013_rc_cal_add()
147 else if (val < 0) in fc0013_rc_cal_add()
148 ret = fc0013_writereg(priv, 0x10, 0x00); in fc0013_rc_cal_add()
150 ret = fc0013_writereg(priv, 0x10, (u8)val); in fc0013_rc_cal_add()
154 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0013_rc_cal_add()
168 ret = fc0013_writereg(priv, 0x0d, 0x01); in fc0013_rc_cal_reset()
170 ret = fc0013_writereg(priv, 0x10, 0x00); in fc0013_rc_cal_reset()
173 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0013_rc_cal_reset()
184 ret = fc0013_readreg(priv, 0x1d, &tmp); in fc0013_set_vhf_track()
187 tmp &= 0xe3; in fc0013_set_vhf_track()
189 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c); in fc0013_set_vhf_track()
191 ret = fc0013_writereg(priv, 0x1d, tmp | 0x18); in fc0013_set_vhf_track()
193 ret = fc0013_writereg(priv, 0x1d, tmp | 0x14); in fc0013_set_vhf_track()
195 ret = fc0013_writereg(priv, 0x1d, tmp | 0x10); in fc0013_set_vhf_track()
197 ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c); in fc0013_set_vhf_track()
199 ret = fc0013_writereg(priv, 0x1d, tmp | 0x08); in fc0013_set_vhf_track()
201 ret = fc0013_writereg(priv, 0x1d, tmp | 0x04); in fc0013_set_vhf_track()
203 ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c); in fc0013_set_vhf_track()
212 int i, ret = 0; in fc0013_set_params()
223 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1)); in fc0013_set_params()
251 ret = fc0013_readreg(priv, 0x07, &tmp); in fc0013_set_params()
254 ret = fc0013_writereg(priv, 0x07, tmp | 0x10); in fc0013_set_params()
259 ret = fc0013_readreg(priv, 0x14, &tmp); in fc0013_set_params()
262 ret = fc0013_writereg(priv, 0x14, tmp & 0x1f); in fc0013_set_params()
267 ret = fc0013_readreg(priv, 0x07, &tmp); in fc0013_set_params()
270 ret = fc0013_writereg(priv, 0x07, tmp & 0xef); in fc0013_set_params()
275 ret = fc0013_readreg(priv, 0x14, &tmp); in fc0013_set_params()
278 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x40); in fc0013_set_params()
283 ret = fc0013_readreg(priv, 0x07, &tmp); in fc0013_set_params()
286 ret = fc0013_writereg(priv, 0x07, tmp & 0xef); in fc0013_set_params()
291 ret = fc0013_readreg(priv, 0x14, &tmp); in fc0013_set_params()
294 ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x20); in fc0013_set_params()
302 reg[5] = 0x82; in fc0013_set_params()
303 reg[6] = 0x00; in fc0013_set_params()
306 reg[5] = 0x02; in fc0013_set_params()
307 reg[6] = 0x02; in fc0013_set_params()
310 reg[5] = 0x42; in fc0013_set_params()
311 reg[6] = 0x00; in fc0013_set_params()
314 reg[5] = 0x82; in fc0013_set_params()
315 reg[6] = 0x02; in fc0013_set_params()
318 reg[5] = 0x22; in fc0013_set_params()
319 reg[6] = 0x00; in fc0013_set_params()
322 reg[5] = 0x42; in fc0013_set_params()
323 reg[6] = 0x02; in fc0013_set_params()
326 reg[5] = 0x12; in fc0013_set_params()
327 reg[6] = 0x00; in fc0013_set_params()
330 reg[5] = 0x22; in fc0013_set_params()
331 reg[6] = 0x02; in fc0013_set_params()
334 reg[5] = 0x0a; in fc0013_set_params()
335 reg[6] = 0x00; in fc0013_set_params()
338 reg[5] = 0x12; in fc0013_set_params()
339 reg[6] = 0x02; in fc0013_set_params()
342 reg[5] = 0x0a; in fc0013_set_params()
343 reg[6] = 0x02; in fc0013_set_params()
349 reg[6] |= 0x08; in fc0013_set_params()
371 reg[1] = 0x06; in fc0013_set_params()
372 reg[2] = 0x11; in fc0013_set_params()
376 reg[6] |= 0x20; in fc0013_set_params()
386 reg[4] = xin & 0xff; in fc0013_set_params()
389 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ in fc0013_set_params()
392 reg[6] |= 0x80; in fc0013_set_params()
395 reg[6] |= 0x40; in fc0013_set_params()
407 reg[5] |= 0x07; in fc0013_set_params()
415 ret = fc0013_readreg(priv, 0x11, &tmp); in fc0013_set_params()
419 ret = fc0013_writereg(priv, 0x11, tmp | 0x04); in fc0013_set_params()
421 ret = fc0013_writereg(priv, 0x11, tmp & 0xfb); in fc0013_set_params()
426 ret = fc0013_writereg(priv, 0x0e, 0x80); in fc0013_set_params()
428 ret = fc0013_writereg(priv, 0x0e, 0x00); in fc0013_set_params()
432 ret = fc0013_writereg(priv, 0x0e, 0x00); in fc0013_set_params()
436 ret = fc0013_readreg(priv, 0x0e, &tmp); in fc0013_set_params()
442 tmp &= 0x3f; in fc0013_set_params()
445 if (tmp > 0x3c) { in fc0013_set_params()
446 reg[6] &= ~0x08; in fc0013_set_params()
447 ret = fc0013_writereg(priv, 0x06, reg[6]); in fc0013_set_params()
449 ret = fc0013_writereg(priv, 0x0e, 0x80); in fc0013_set_params()
451 ret = fc0013_writereg(priv, 0x0e, 0x00); in fc0013_set_params()
454 if (tmp < 0x02) { in fc0013_set_params()
455 reg[6] |= 0x08; in fc0013_set_params()
456 ret = fc0013_writereg(priv, 0x06, reg[6]); in fc0013_set_params()
458 ret = fc0013_writereg(priv, 0x0e, 0x80); in fc0013_set_params()
460 ret = fc0013_writereg(priv, 0x0e, 0x00); in fc0013_set_params()
469 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0013_set_params()
479 return 0; in fc0013_get_frequency()
485 *frequency = 0; in fc0013_get_if_frequency()
486 return 0; in fc0013_get_if_frequency()
493 return 0; in fc0013_get_bandwidth()
519 ret = fc0013_writereg(priv, 0x13, 0x00); in fc0013_get_rf_strength()
523 ret = fc0013_readreg(priv, 0x13, &tmp); in fc0013_get_rf_strength()
528 ret = fc0013_readreg(priv, 0x14, &tmp); in fc0013_get_rf_strength()
531 lna_gain = tmp & 0x1f; in fc0013_get_rf_strength()
534 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0013_get_rf_strength()
539 (int_temp & 0x1f)) * 2; in fc0013_get_rf_strength()
545 *strength = 0; in fc0013_get_rf_strength()
558 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ in fc0013_get_rf_strength()