Lines Matching +full:low +full:- +full:power +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
40 /* enable rx */
53 /* enable tx FIFO space available interrupt */
89 /* rx low carrier frequency, in Hz, 0 means no demodulation */
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
133 * From two limit frequencies, L (low) and H (high), we can get both the
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
170 * Environment Control - Low Pin Count Input / Output
171 * (EC - LPC I/O)
177 #define IT87_IER 0x01 /* interrupt enable register */
183 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
190 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
191 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
192 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
193 #define IT87_IEC 0x08 /* interrupt enable control */
194 #define IT87_BR 0x10 /* baud rate register enable */
200 #define IT87_RXEND 0x10 /* receiver demodulation enable */
201 #define IT87_RXEN 0x20 /* receiver enable */
202 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
209 #define IT87_TXRLE 0x08 /* transmitter run length enable */
212 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 * 0x30 -> 25 */
214 #define IT87_ILE 0x40 /* internal loopback enable */
228 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
234 #define IT87_II_TXLDL 0x02 /* transmitter low data level */
259 #define IT85_C0IER 0x02 /* interrupt enable register */
265 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
271 #define IT85_C0WPS 0x0f /* wakeup power control/status register */
280 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 * 0x0c -> 25 */
282 #define IT85_ILE 0x10 /* internal loopback enable */
286 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
287 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */
288 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
289 #define IT85_IEC 0x80 /* interrupt enable function control */
292 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
304 #define IT85_RXEND 0x10 /* receiver demodulation enable */
306 #define IT85_RXEN 0x80 /* receiver enable */
314 #define IT85_TXRLE 0x40 /* transmitter run length enable */
319 #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */
320 #define IT85_DLLTE 0x08 /* DLL test enable */
329 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
335 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
336 #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */
337 #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */
349 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350 * selectable by a single bank-select bit that's mapped onto both banks. The
353 * reserved high-order bit are placed at the same offset in both banks in
361 #define IT8708_HRAE 0x80 /* high registers access enable */
363 /* mapped onto the low bank */
366 #define IT8708_C0IER 0x02 /* interrupt enable register */
374 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
384 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */
408 * a specific firmware running on the IT8512's embedded micro-controller.
409 * In addition of the embedded micro-controller, the IT8512 chip contains a
412 * micro-controller. The CIR module is only accessible by the
413 * micro-controller.
415 * The battery-backed SRAM module is accessible by the host CPU and the
416 * micro-controller. So one of the MC's firmware role is to act as a bridge
420 * communication protocol is not, so it was reverse-engineered.