Lines Matching +full:data +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
82 /* sync data */
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
125 /* convert bits to us */
126 #define ITE_BITS_TO_US(bits, sample_period) \ argument
127 ((u32)((bits) * ITE_BAUDRATE_DIVISOR * (sample_period) / 1000))
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
158 /* DR TX bits */
167 * hardware data obtained from:
170 * Environment Control - Low Pin Count Input / Output
171 * (EC - LPC I/O)
176 #define IT87_DR 0x00 /* data register */
189 /* IER bits */
190 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
191 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
197 /* RCR bits */
202 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
203 #define IT87_RDWOS 0x80 /* receiver data without sync */
205 /* TCR1 bits */
212 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 * 0x30 -> 25 */
217 /* TCR2 bits */
223 /* TSR bits */
226 /* RSR bits */
228 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
230 /* IIR bits */
234 #define IT87_II_TXLDL 0x02 /* transmitter low data level */
235 #define IT87_II_RXDS 0x04 /* receiver data stored */
241 * Hardware data obtained from:
257 #define IT85_C0DR 0x00 /* data register */
275 /* C0MSTCR bits */
280 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 * 0x0c -> 25 */
285 /* C0IER bits */
286 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
287 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */
291 /* C0IIR bits */
292 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
293 #define IT85_RDAI 0x02 /* receiver data available interrupt */
297 /* C0CFR bits */
301 /* C0RCR bits */
305 #define IT85_RDWOS 0x20 /* receiver data without sync */
308 /* C0TCR bits */
316 /* C0SCK bits */
324 /* C0TFSR bits */
327 /* C0RFSR bits */
329 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
331 /* C0WCL bits */
334 /* C0WPS bits */
344 * Hardware data obtained from hacked driver for IT8512 in this forum post:
349 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350 * selectable by a single bank-select bit that's mapped onto both banks. The
353 * reserved high-order bit are placed at the same offset in both banks in
364 #define IT8708_C0DR 0x00 /* data register */
389 * found in the data sheets; no idea what they are or how they are accessed,
394 /* CSCRR bits */
398 /* CGPINTR bits */
404 * Hardware interfacing data obtained from the original lirc_ite8709 driver.
408 * a specific firmware running on the IT8512's embedded micro-controller.
409 * In addition of the embedded micro-controller, the IT8512 chip contains a
412 * micro-controller. The CIR module is only accessible by the
413 * micro-controller.
415 * The battery-backed SRAM module is accessible by the host CPU and the
416 * micro-controller. So one of the MC's firmware role is to act as a bridge
420 * communication protocol is not, so it was reverse-engineered.
425 #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */