3  * Hantro VPU codec driver
282 	struct hantro_dev *vpu = dev_id;  in rockchip_vpu1_vepu_irq()  local
286 	status = vepu_read(vpu, H1_REG_INTERRUPT);  in rockchip_vpu1_vepu_irq()
290 	vepu_write(vpu, 0, H1_REG_INTERRUPT);  in rockchip_vpu1_vepu_irq()
291 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);  in rockchip_vpu1_vepu_irq()
293 	hantro_irq_done(vpu, state);  in rockchip_vpu1_vepu_irq()
300 	struct hantro_dev *vpu = dev_id;  in rockchip_vpu2_vdpu_irq()  local
304 	status = vdpu_read(vpu, VDPU_REG_INTERRUPT);  in rockchip_vpu2_vdpu_irq()
308 	vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);  in rockchip_vpu2_vdpu_irq()
309 	vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);  in rockchip_vpu2_vdpu_irq()
311 	hantro_irq_done(vpu, state);  in rockchip_vpu2_vdpu_irq()
318 	struct hantro_dev *vpu = dev_id;  in rockchip_vpu2_vepu_irq()  local
322 	status = vepu_read(vpu, VEPU_REG_INTERRUPT);  in rockchip_vpu2_vepu_irq()
326 	vepu_write(vpu, 0, VEPU_REG_INTERRUPT);  in rockchip_vpu2_vepu_irq()
327 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);  in rockchip_vpu2_vepu_irq()
329 	hantro_irq_done(vpu, state);  in rockchip_vpu2_vepu_irq()
334 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)  in rk3036_vpu_hw_init()  argument
337 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);  in rk3036_vpu_hw_init()
341 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)  in rk3066_vpu_hw_init()  argument
344 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);  in rk3066_vpu_hw_init()
345 	clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);  in rk3066_vpu_hw_init()
349 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)  in rockchip_vpu_hw_init()  argument
352 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);  in rockchip_vpu_hw_init()
358 	struct hantro_dev *vpu = ctx->dev;  in rk3066_vpu_dec_reset()  local
360 	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);  in rk3066_vpu_dec_reset()
361 	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);  in rk3066_vpu_dec_reset()
366 	struct hantro_dev *vpu = ctx->dev;  in rockchip_vpu1_enc_reset()  local
368 	vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);  in rockchip_vpu1_enc_reset()
369 	vepu_write(vpu, 0, H1_REG_ENC_CTRL);  in rockchip_vpu1_enc_reset()
370 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);  in rockchip_vpu1_enc_reset()
375 	struct hantro_dev *vpu = ctx->dev;  in rockchip_vpu2_dec_reset()  local
377 	vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);  in rockchip_vpu2_dec_reset()
378 	vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);  in rockchip_vpu2_dec_reset()
379 	vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);  in rockchip_vpu2_dec_reset()
384 	struct hantro_dev *vpu = ctx->dev;  in rockchip_vpu2_enc_reset()  local
386 	vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);  in rockchip_vpu2_enc_reset()
387 	vepu_write(vpu, 0, VEPU_REG_ENCODE_START);  in rockchip_vpu2_enc_reset()
388 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);  in rockchip_vpu2_enc_reset()
502  * VPU variant.