17 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \  argument
19 	hantro_reg_write(vpu, \
24 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \  argument
26 	hantro_reg_write_s(vpu, \
65 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_g1_enable()  local
71 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);  in hantro_postproc_g1_enable()
89 	HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);  in hantro_postproc_g1_enable()
90 	HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);  in hantro_postproc_g1_enable()
91 	HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);  in hantro_postproc_g1_enable()
92 	HANTRO_PP_REG_WRITE(vpu, max_burst, 16);  in hantro_postproc_g1_enable()
93 	HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma);  in hantro_postproc_g1_enable()
94 	HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width));  in hantro_postproc_g1_enable()
95 	HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height));  in hantro_postproc_g1_enable()
96 	HANTRO_PP_REG_WRITE(vpu, input_fmt, src_pp_fmt);  in hantro_postproc_g1_enable()
97 	HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt);  in hantro_postproc_g1_enable()
98 	HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width);  in hantro_postproc_g1_enable()
99 	HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);  in hantro_postproc_g1_enable()
100 	HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));  in hantro_postproc_g1_enable()
101 	HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);  in hantro_postproc_g1_enable()
114 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_g2_enable()  local
127 		hantro_reg_write(vpu, &g2_down_scale_e, 1);  in hantro_postproc_g2_enable()
128 		hantro_reg_write(vpu, &g2_down_scale_y, down_scale >> 2);  in hantro_postproc_g2_enable()
129 		hantro_reg_write(vpu, &g2_down_scale_x, down_scale >> 2);  in hantro_postproc_g2_enable()
130 		hantro_write_addr(vpu, G2_DS_DST, dst_dma);  in hantro_postproc_g2_enable()
131 		hantro_write_addr(vpu, G2_DS_DST_CHR, dst_dma + (chroma_offset >> down_scale));  in hantro_postproc_g2_enable()
133 		hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);  in hantro_postproc_g2_enable()
134 		hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset);  in hantro_postproc_g2_enable()
147 		hantro_reg_write(vpu, &g2_output_8_bits, out_depth > 8 ? 0 : 1);  in hantro_postproc_g2_enable()
148 		hantro_reg_write(vpu, &g2_output_format, out_depth > 8 ? 1 : 0);  in hantro_postproc_g2_enable()
150 	hantro_reg_write(vpu, &g2_out_rs_e, 1);  in hantro_postproc_g2_enable()
175 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_free()  local
182 			dma_free_attrs(vpu->dev, priv->size, priv->cpu,  in hantro_postproc_free()
191 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_alloc()  local
225 		priv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &priv->dma,  in hantro_postproc_alloc()
236 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_g1_disable()  local
238 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);  in hantro_postproc_g1_disable()
243 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_g2_disable()  local
245 	hantro_reg_write(vpu, &g2_out_rs_e, 0);  in hantro_postproc_g2_disable()
250 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_disable()  local
252 	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable)  in hantro_postproc_disable()
253 		vpu->variant->postproc_ops->disable(ctx);  in hantro_postproc_disable()
258 	struct hantro_dev *vpu = ctx->dev;  in hantro_postproc_enable()  local
260 	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable)  in hantro_postproc_enable()
261 		vpu->variant->postproc_ops->enable(ctx);  in hantro_postproc_enable()
267 	struct hantro_dev *vpu = ctx->dev;  in hanto_postproc_enum_framesizes()  local
269 	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enum_framesizes)  in hanto_postproc_enum_framesizes()
270 		return vpu->variant->postproc_ops->enum_framesizes(ctx, fsize);  in hanto_postproc_enum_framesizes()