Lines Matching +full:post +full:- +full:processing

1 /* SPDX-License-Identifier: GPL-2.0 */
8  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-core.h>
26 #include <media/videobuf2-dma-contig.h>
44  * struct hantro_irq - irq handler and name
55  * struct hantro_variant - information about VPU hardware variant
63  * @postproc_fmts:		Post-processor formats.
64  * @num_postproc_fmts:		Number of post-processor formats.
65  * @postproc_ops:		Post-processor ops.
106  * enum hantro_codec_mode - codec operating mode.
110  * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
116 	HANTRO_MODE_NONE = -1,
126  * struct hantro_ctrl - helper type to declare supported controls
136  * struct hantro_func - Hantro VPU functionality
138  * @id:			processing functionality ID (can be
171  * struct hantro_dev - driver data
189  * @variant:		Hardware variant-specific parameters.
214  * struct hantro_ctx - Context (instance) private data.
229  * @jpeg_quality:	User-specified JPEG compression quality.
233  * @postproc:		Post-processing context.
234  * @h264_dec:		H.264-decoding context.
235  * @jpeg_enc:		JPEG-encoding context.
236  * @mpeg2_dec:		MPEG-2-decoding context.
237  * @vp8_dec:		VP8-decoding context.
238  * @hevc_dec:		HEVC-decoding context.
239  * @vp9_dec:		VP9-decoding context.
272  * struct hantro_fmt - information about supported video formats.
281  * @postprocessed: Indicates if this format needs the post-processor.
344  * bit 0 - global information: mode, size, init, release
345  * bit 1 - each run start/result information
346  * bit 2 - contents of small controls from userspace
347  * bit 3 - contents of big controls from userspace
348  * bit 4 - detail fmt, ctrl, buffer q/dq information
349  * bit 5 - detail function enter/leave trace information
350  * bit 6 - register write/read information
375 	writel_relaxed(val, vpu->enc_base + reg);  in vepu_write_relaxed()
381 	writel(val, vpu->enc_base + reg);  in vepu_write()
386 	u32 val = readl(vpu->enc_base + reg);  in vepu_read()
396 	writel_relaxed(val, vpu->dec_base + reg);  in vdpu_write_relaxed()
402 	writel(val, vpu->dec_base + reg);  in vdpu_write()
414 	u32 val = readl(vpu->dec_base + reg);  in vdpu_read()
426 	v = vdpu_read(vpu, reg->base);  in vdpu_read_mask()
427 	v &= ~(reg->mask << reg->shift);  in vdpu_read_mask()
428 	v |= ((val & reg->mask) << reg->shift);  in vdpu_read_mask()
436 	vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);  in hantro_reg_write()
443 	vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);  in hantro_reg_write_s()
452 	return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);  in hantro_get_src_buf()
458 	return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);  in hantro_get_dst_buf()
467 	if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))  in hantro_get_dec_buf_addr()
468 		return ctx->postproc.dec_q[vb->index].dma;  in hantro_get_dec_buf_addr()