Lines Matching +full:32 +full:- +full:rail
1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CCP2 module
62 * ccp2_print_status - Print current CCP2 module register values.
65 dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
72 dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n"); in ccp2_print_status()
103 dev_dbg(isp->dev, "--------------------------------------------\n"); in ccp2_print_status()
107 * ccp2_reset - Reset the CCP2
122 dev_warn(isp->dev, in ccp2_reset()
130 * ccp2_pwr_cfg - Configure the power mode settings
138 ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ? in ccp2_pwr_cfg()
144 * ccp2_if_enable - Enable CCP2 interface.
154 if (enable && ccp2->vdds_csib) { in ccp2_if_enable()
155 ret = regulator_enable(ccp2->vdds_csib); in ccp2_if_enable()
171 if (!enable && ccp2->vdds_csib) in ccp2_if_enable()
172 regulator_disable(ccp2->vdds_csib); in ccp2_if_enable()
178 * ccp2_mem_enable - Enable CCP2 memory interface.
199 * ccp2_phyif_config - Initialize CCP2 phy interface config
205 * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
217 buscfg->phy_layer); in ccp2_phyif_config()
219 ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode); in ccp2_phyif_config()
221 buscfg->strobe_clk_pol); in ccp2_phyif_config()
223 ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol); in ccp2_phyif_config()
228 if (buscfg->ccp2_mode == ISP_CCP2_MODE_CCP2) in ccp2_phyif_config()
229 dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n"); in ccp2_phyif_config()
230 if (buscfg->phy_layer == ISP_CCP2_PHY_DATA_STROBE) in ccp2_phyif_config()
232 return -EIO; in ccp2_phyif_config()
239 * ccp2_vp_config - Initialize CCP2 video port interface.
246 * - revision 1.0 and 2.0 1 to 4
247 * - revision 15.0 1 to 65536
262 if (isp->revision == ISP_REVISION_15_0) { in ccp2_vp_config()
270 ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1); in ccp2_vp_config()
277 * ccp2_lcx_config - Initialize CCP2 logical channel interface.
291 switch (config->format) { in ccp2_lcx_config()
304 if (isp->revision == ISP_REVISION_15_0) { in ccp2_lcx_config()
308 config->crc); in ccp2_lcx_config()
315 config->crc); in ccp2_lcx_config()
323 isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT, in ccp2_lcx_config()
327 isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT, in ccp2_lcx_config()
343 * ccp2_if_configure - Configure ccp2 with data from sensor
350 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity); in ccp2_if_configure()
360 pad = media_pad_remote_pad_first(&ccp2->pads[CCP2_PAD_SINK]); in ccp2_if_configure()
361 sensor = media_entity_to_v4l2_subdev(pad->entity); in ccp2_if_configure()
362 buscfg = v4l2_subdev_to_bus_cfg(pipe->external); in ccp2_if_configure()
364 ret = ccp2_phyif_config(ccp2, &buscfg->bus.ccp2); in ccp2_if_configure()
368 ccp2_vp_config(ccp2, buscfg->bus.ccp2.vpclk_div + 1); in ccp2_if_configure()
372 format = &ccp2->formats[CCP2_PAD_SINK]; in ccp2_if_configure()
374 ccp2->if_cfg.data_start = lines; in ccp2_if_configure()
375 ccp2->if_cfg.crc = buscfg->bus.ccp2.crc; in ccp2_if_configure()
376 ccp2->if_cfg.format = format->code; in ccp2_if_configure()
377 ccp2->if_cfg.data_size = format->height; in ccp2_if_configure()
379 ccp2_lcx_config(ccp2, &ccp2->if_cfg); in ccp2_if_configure()
386 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity); in ccp2_adjust_bandwidth()
388 const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE]; in ccp2_adjust_bandwidth()
389 unsigned long l3_ick = pipe->l3_ick; in ccp2_adjust_bandwidth()
400 vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate), in ccp2_adjust_bandwidth()
407 timeperframe = &pipe->max_timeperframe; in ccp2_adjust_bandwidth()
409 if (timeperframe->numerator) { in ccp2_adjust_bandwidth()
410 area = ofmt->width * ofmt->height; in ccp2_adjust_bandwidth()
411 bound = div_u64(area * timeperframe->denominator, in ccp2_adjust_bandwidth()
412 timeperframe->numerator); in ccp2_adjust_bandwidth()
417 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__, in ccp2_adjust_bandwidth()
424 * ccp2_mem_configure - Initialize CCP2 memory input/output interface
436 u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code; in ccp2_mem_configure()
437 u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code; in ccp2_mem_configure()
449 (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT), in ccp2_mem_configure()
453 isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT, in ccp2_mem_configure()
456 if (ccp2->video_in.bpl_padding == 0) in ccp2_mem_configure()
457 config->src_ofst = 0; in ccp2_mem_configure()
459 config->src_ofst = ccp2->video_in.bpl_value; in ccp2_mem_configure()
461 isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2, in ccp2_mem_configure()
473 /* RAW8 + DPCM10 - simple predictor */ in ccp2_mem_configure()
485 /* Burst size to 32x64 */ in ccp2_mem_configure()
494 config->hsize_count) >> 3; in ccp2_mem_configure()
497 config->hsize_count) >> 2; in ccp2_mem_configure()
519 * ccp2_set_inaddr - Sets memory address of input frame.
521 * @addr: 32bit memory address aligned on 32byte boundary.
532 /* -----------------------------------------------------------------------------
538 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity); in ccp2_isr_buffer()
541 buffer = omap3isp_video_buffer_next(&ccp2->video_in); in ccp2_isr_buffer()
543 ccp2_set_inaddr(ccp2, buffer->dma); in ccp2_isr_buffer()
545 pipe->state |= ISP_PIPELINE_IDLE_INPUT; in ccp2_isr_buffer()
547 if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) { in ccp2_isr_buffer()
555 * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
562 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity); in omap3isp_ccp2_isr()
585 pipe->error = true; in omap3isp_ccp2_isr()
586 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus); in omap3isp_ccp2_isr()
591 pipe->error = true; in omap3isp_ccp2_isr()
592 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus); in omap3isp_ccp2_isr()
595 if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping)) in omap3isp_ccp2_isr()
603 /* -----------------------------------------------------------------------------
613 * __ccp2_get_format - helper function for getting ccp2 format
626 return v4l2_subdev_get_try_format(&ccp2->subdev, sd_state, in __ccp2_get_format()
629 return &ccp2->formats[pad]; in __ccp2_get_format()
633 * ccp2_try_format - Handle try format by pad subdev method
650 if (fmt->code != MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8) in ccp2_try_format()
651 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; in ccp2_try_format()
653 if (ccp2->input == CCP2_INPUT_SENSOR) { in ccp2_try_format()
654 fmt->width = clamp_t(u32, fmt->width, in ccp2_try_format()
657 fmt->height = clamp_t(u32, fmt->height, in ccp2_try_format()
660 } else if (ccp2->input == CCP2_INPUT_MEMORY) { in ccp2_try_format()
661 fmt->width = clamp_t(u32, fmt->width, in ccp2_try_format()
664 fmt->height = clamp_t(u32, fmt->height, in ccp2_try_format()
671 /* Source format - copy sink format and change pixel code in ccp2_try_format()
679 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; in ccp2_try_format()
683 fmt->field = V4L2_FIELD_NONE; in ccp2_try_format()
684 fmt->colorspace = V4L2_COLORSPACE_SRGB; in ccp2_try_format()
688 * ccp2_enum_mbus_code - Handle pixel format enumeration
692 * return -EINVAL or zero on success
701 if (code->pad == CCP2_PAD_SINK) { in ccp2_enum_mbus_code()
702 if (code->index >= ARRAY_SIZE(ccp2_fmts)) in ccp2_enum_mbus_code()
703 return -EINVAL; in ccp2_enum_mbus_code()
705 code->code = ccp2_fmts[code->index]; in ccp2_enum_mbus_code()
707 if (code->index != 0) in ccp2_enum_mbus_code()
708 return -EINVAL; in ccp2_enum_mbus_code()
711 code->which); in ccp2_enum_mbus_code()
712 code->code = format->code; in ccp2_enum_mbus_code()
725 if (fse->index != 0) in ccp2_enum_frame_size()
726 return -EINVAL; in ccp2_enum_frame_size()
728 format.code = fse->code; in ccp2_enum_frame_size()
731 ccp2_try_format(ccp2, sd_state, fse->pad, &format, fse->which); in ccp2_enum_frame_size()
732 fse->min_width = format.width; in ccp2_enum_frame_size()
733 fse->min_height = format.height; in ccp2_enum_frame_size()
735 if (format.code != fse->code) in ccp2_enum_frame_size()
736 return -EINVAL; in ccp2_enum_frame_size()
738 format.code = fse->code; in ccp2_enum_frame_size()
739 format.width = -1; in ccp2_enum_frame_size()
740 format.height = -1; in ccp2_enum_frame_size()
741 ccp2_try_format(ccp2, sd_state, fse->pad, &format, fse->which); in ccp2_enum_frame_size()
742 fse->max_width = format.width; in ccp2_enum_frame_size()
743 fse->max_height = format.height; in ccp2_enum_frame_size()
749 * ccp2_get_format - Handle get format by pads subdev method
753 * return -EINVAL or zero on success
762 format = __ccp2_get_format(ccp2, sd_state, fmt->pad, fmt->which); in ccp2_get_format()
764 return -EINVAL; in ccp2_get_format()
766 fmt->format = *format; in ccp2_get_format()
771 * ccp2_set_format - Handle set format by pads subdev method
784 format = __ccp2_get_format(ccp2, sd_state, fmt->pad, fmt->which); in ccp2_set_format()
786 return -EINVAL; in ccp2_set_format()
788 ccp2_try_format(ccp2, sd_state, fmt->pad, &fmt->format, fmt->which); in ccp2_set_format()
789 *format = fmt->format; in ccp2_set_format()
792 if (fmt->pad == CCP2_PAD_SINK) { in ccp2_set_format()
794 fmt->which); in ccp2_set_format()
795 *format = fmt->format; in ccp2_set_format()
797 fmt->which); in ccp2_set_format()
804 * ccp2_init_formats - Initialize formats on all pads
822 ccp2_set_format(sd, fh ? fh->state : NULL, &format); in ccp2_init_formats()
828 * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
840 if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) { in ccp2_s_stream()
843 atomic_set(&ccp2->stopping, 0); in ccp2_s_stream()
848 if (ccp2->phy) { in ccp2_s_stream()
849 ret = omap3isp_csiphy_acquire(ccp2->phy, &sd->entity); in ccp2_s_stream()
860 if (ccp2->phy) in ccp2_s_stream()
861 omap3isp_csiphy_release(ccp2->phy); in ccp2_s_stream()
867 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) { in ccp2_s_stream()
870 format = &ccp2->formats[CCP2_PAD_SINK]; in ccp2_s_stream()
872 ccp2->mem_cfg.hsize_count = format->width; in ccp2_s_stream()
873 ccp2->mem_cfg.vsize_count = format->height; in ccp2_s_stream()
874 ccp2->mem_cfg.src_ofst = 0; in ccp2_s_stream()
876 ccp2_mem_configure(ccp2, &ccp2->mem_cfg); in ccp2_s_stream()
884 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait, in ccp2_s_stream()
885 &ccp2->stopping)) in ccp2_s_stream()
886 dev_dbg(dev, "%s: module stop timeout.\n", sd->name); in ccp2_s_stream()
887 if (ccp2->input == CCP2_INPUT_MEMORY) { in ccp2_s_stream()
890 } else if (ccp2->input == CCP2_INPUT_SENSOR) { in ccp2_s_stream()
893 if (ccp2->phy) in ccp2_s_stream()
894 omap3isp_csiphy_release(ccp2->phy); in ccp2_s_stream()
899 ccp2->state = enable; in ccp2_s_stream()
927 /* --------------------------------------------------------------------------
932 * ccp2_video_queue - Queue video buffer.
935 * return -EIO or zero on success
939 struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2; in ccp2_video_queue()
941 ccp2_set_inaddr(ccp2, buffer->dma); in ccp2_video_queue()
949 /* -----------------------------------------------------------------------------
954 * ccp2_link_setup - Setup ccp2 connections.
959 * return -EINVAL on error or zero on success
967 unsigned int index = local->index; in ccp2_link_setup()
970 if (is_media_entity_v4l2_subdev(remote->entity)) in ccp2_link_setup()
977 if (ccp2->input == CCP2_INPUT_SENSOR) in ccp2_link_setup()
978 return -EBUSY; in ccp2_link_setup()
979 ccp2->input = CCP2_INPUT_MEMORY; in ccp2_link_setup()
981 if (ccp2->input == CCP2_INPUT_MEMORY) in ccp2_link_setup()
982 ccp2->input = CCP2_INPUT_NONE; in ccp2_link_setup()
989 if (ccp2->input == CCP2_INPUT_MEMORY) in ccp2_link_setup()
990 return -EBUSY; in ccp2_link_setup()
991 ccp2->input = CCP2_INPUT_SENSOR; in ccp2_link_setup()
993 if (ccp2->input == CCP2_INPUT_SENSOR) in ccp2_link_setup()
994 ccp2->input = CCP2_INPUT_NONE; in ccp2_link_setup()
1000 ccp2->output = CCP2_OUTPUT_CCDC; in ccp2_link_setup()
1002 ccp2->output = CCP2_OUTPUT_NONE; in ccp2_link_setup()
1006 return -EINVAL; in ccp2_link_setup()
1019 * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1024 v4l2_device_unregister_subdev(&ccp2->subdev); in omap3isp_ccp2_unregister_entities()
1025 omap3isp_video_unregister(&ccp2->video_in); in omap3isp_ccp2_unregister_entities()
1029 * omap3isp_ccp2_register_entities - Register the subdev media entity
1041 ccp2->subdev.dev = vdev->mdev->dev; in omap3isp_ccp2_register_entities()
1042 ret = v4l2_device_register_subdev(vdev, &ccp2->subdev); in omap3isp_ccp2_register_entities()
1046 ret = omap3isp_video_register(&ccp2->video_in, vdev); in omap3isp_ccp2_register_entities()
1057 /* -----------------------------------------------------------------------------
1062 * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1068 struct v4l2_subdev *sd = &ccp2->subdev; in ccp2_init_entities()
1069 struct media_pad *pads = ccp2->pads; in ccp2_init_entities()
1070 struct media_entity *me = &sd->entity; in ccp2_init_entities()
1073 ccp2->input = CCP2_INPUT_NONE; in ccp2_init_entities()
1074 ccp2->output = CCP2_OUTPUT_NONE; in ccp2_init_entities()
1077 sd->internal_ops = &ccp2_sd_internal_ops; in ccp2_init_entities()
1078 strscpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name)); in ccp2_init_entities()
1079 sd->grp_id = 1 << 16; /* group ID for isp subdevs */ in ccp2_init_entities()
1081 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; in ccp2_init_entities()
1087 me->ops = &ccp2_media_ops; in ccp2_init_entities()
1099 * padded line length must be a multiple of 32 bytes. To simplify the in ccp2_init_entities()
1100 * implementation we use a fixed 32 bytes alignment regardless of the in ccp2_init_entities()
1105 ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; in ccp2_init_entities()
1106 ccp2->video_in.bpl_alignment = 32; in ccp2_init_entities()
1107 ccp2->video_in.bpl_max = 0xffffffe0; in ccp2_init_entities()
1108 ccp2->video_in.isp = to_isp_device(ccp2); in ccp2_init_entities()
1109 ccp2->video_in.ops = &ccp2_video_ops; in ccp2_init_entities()
1110 ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3; in ccp2_init_entities()
1112 ret = omap3isp_video_init(&ccp2->video_in, "CCP2"); in ccp2_init_entities()
1119 media_entity_cleanup(&ccp2->subdev.entity); in ccp2_init_entities()
1124 * omap3isp_ccp2_init - CCP2 initialization.
1130 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2; in omap3isp_ccp2_init()
1133 init_waitqueue_head(&ccp2->wait); in omap3isp_ccp2_init()
1137 * complex, which is powered by vdds_csib power rail. Hence the in omap3isp_ccp2_init()
1146 if (isp->revision == ISP_REVISION_2_0) { in omap3isp_ccp2_init()
1147 ccp2->vdds_csib = devm_regulator_get(isp->dev, "vdds_csib"); in omap3isp_ccp2_init()
1148 if (IS_ERR(ccp2->vdds_csib)) { in omap3isp_ccp2_init()
1149 if (PTR_ERR(ccp2->vdds_csib) == -EPROBE_DEFER) { in omap3isp_ccp2_init()
1150 dev_dbg(isp->dev, in omap3isp_ccp2_init()
1152 return -EPROBE_DEFER; in omap3isp_ccp2_init()
1154 dev_dbg(isp->dev, in omap3isp_ccp2_init()
1156 ccp2->vdds_csib = NULL; in omap3isp_ccp2_init()
1158 ccp2->phy = &isp->isp_csiphy2; in omap3isp_ccp2_init()
1159 } else if (isp->revision == ISP_REVISION_15_0) { in omap3isp_ccp2_init()
1160 ccp2->phy = &isp->isp_csiphy1; in omap3isp_ccp2_init()
1172 * omap3isp_ccp2_cleanup - CCP2 un-initialization
1177 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2; in omap3isp_ccp2_cleanup()
1179 omap3isp_video_cleanup(&ccp2->video_in); in omap3isp_ccp2_cleanup()
1180 media_entity_cleanup(&ccp2->subdev.entity); in omap3isp_ccp2_cleanup()