Lines Matching +full:0 +full:x3b00
17 #define VI6_CMD(n) (0x0000 + (n) * 4)
19 #define VI6_CMD_STRCMD BIT(0)
21 #define VI6_CLK_DCSWT 0x0018
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
24 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0)
25 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0
27 #define VI6_SRESET 0x0028
30 #define VI6_STATUS 0x0038
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12)
36 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
38 #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12)
40 #define VI6_WPF_IRQ_STA_FRE BIT(0)
42 #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60)
47 #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60)
52 #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4)
53 #define VI6_WPF_LINE_COUNT_MASK (0x1fffff << 0)
59 #define VI6_DL_CTRL 0x0100
60 #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16)
67 #define VI6_DL_CTRL_DLE BIT(0)
69 #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4)
71 #define VI6_DL_SWAP 0x0114
74 #define VI6_DL_SWAP_BTS BIT(0)
76 #define VI6_DL_EXT_CTRL(n) (0x011c + (n) * 36)
78 #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8)
82 #define VI6_DL_EXT_CTRL_EXT BIT(0)
84 #define VI6_DL_EXT_AUTOFLD_INT BIT(0)
86 #define VI6_DL_BODY_SIZE 0x0120
88 #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0)
89 #define VI6_DL_BODY_SIZE_BS_SHIFT 0
95 #define VI6_RPF_OFFSET 0x100
97 #define VI6_RPF_SRC_BSIZE 0x0300
98 #define VI6_RPF_SRC_BSIZE_BHSIZE_MASK (0x1fff << 16)
100 #define VI6_RPF_SRC_BSIZE_BVSIZE_MASK (0x1fff << 0)
101 #define VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT 0
103 #define VI6_RPF_SRC_ESIZE 0x0304
104 #define VI6_RPF_SRC_ESIZE_EHSIZE_MASK (0x1fff << 16)
106 #define VI6_RPF_SRC_ESIZE_EVSIZE_MASK (0x1fff << 0)
107 #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0
109 #define VI6_RPF_INFMT 0x0308
114 #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12)
118 #define VI6_RPF_INFMT_RDTM_BT601 (0 << 9)
124 #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0)
125 #define VI6_RPF_INFMT_RDFMT_SHIFT 0
127 #define VI6_RPF_DSWAP 0x030c
135 #define VI6_RPF_DSWAP_P_BTS BIT(0)
137 #define VI6_RPF_LOC 0x0310
138 #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16)
140 #define VI6_RPF_LOC_VCOORD_MASK (0x1fff << 0)
141 #define VI6_RPF_LOC_VCOORD_SHIFT 0
143 #define VI6_RPF_ALPH_SEL 0x0314
144 #define VI6_RPF_ALPH_SEL_ASEL_PACKED (0 << 28)
151 #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24)
154 #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18)
158 #define VI6_RPF_ALPH_SEL_ALPHA1_MASK (0xff << 8)
160 #define VI6_RPF_ALPH_SEL_ALPHA0_MASK (0xff << 0)
161 #define VI6_RPF_ALPH_SEL_ALPHA0_SHIFT 0
163 #define VI6_RPF_VRTCOL_SET 0x0318
164 #define VI6_RPF_VRTCOL_SET_LAYA_MASK (0xff << 24)
166 #define VI6_RPF_VRTCOL_SET_LAYR_MASK (0xff << 16)
168 #define VI6_RPF_VRTCOL_SET_LAYG_MASK (0xff << 8)
170 #define VI6_RPF_VRTCOL_SET_LAYB_MASK (0xff << 0)
171 #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0
173 #define VI6_RPF_MSK_CTRL 0x031c
175 #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16)
177 #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8)
179 #define VI6_RPF_MSK_CTRL_MGB_MASK (0xff << 0)
180 #define VI6_RPF_MSK_CTRL_MGB_SHIFT 0
182 #define VI6_RPF_MSK_SET0 0x0320
183 #define VI6_RPF_MSK_SET1 0x0324
184 #define VI6_RPF_MSK_SET_MSA_MASK (0xff << 24)
186 #define VI6_RPF_MSK_SET_MSR_MASK (0xff << 16)
188 #define VI6_RPF_MSK_SET_MSG_MASK (0xff << 8)
190 #define VI6_RPF_MSK_SET_MSB_MASK (0xff << 0)
191 #define VI6_RPF_MSK_SET_MSB_SHIFT 0
193 #define VI6_RPF_CKEY_CTRL 0x0328
196 #define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0)
198 #define VI6_RPF_CKEY_SET0 0x032c
199 #define VI6_RPF_CKEY_SET1 0x0330
200 #define VI6_RPF_CKEY_SET_AP_MASK (0xff << 24)
202 #define VI6_RPF_CKEY_SET_R_MASK (0xff << 16)
204 #define VI6_RPF_CKEY_SET_GY_MASK (0xff << 8)
206 #define VI6_RPF_CKEY_SET_B_MASK (0xff << 0)
207 #define VI6_RPF_CKEY_SET_B_SHIFT 0
209 #define VI6_RPF_SRCM_PSTRIDE 0x0334
211 #define VI6_RPF_SRCM_PSTRIDE_C_SHIFT 0
213 #define VI6_RPF_SRCM_ASTRIDE 0x0338
214 #define VI6_RPF_SRCM_PSTRIDE_A_SHIFT 0
216 #define VI6_RPF_SRCM_ADDR_Y 0x033c
217 #define VI6_RPF_SRCM_ADDR_C0 0x0340
218 #define VI6_RPF_SRCM_ADDR_C1 0x0344
219 #define VI6_RPF_SRCM_ADDR_AI 0x0348
221 #define VI6_RPF_MULT_ALPHA 0x036c
222 #define VI6_RPF_MULT_ALPHA_A_MMD_NONE (0 << 12)
224 #define VI6_RPF_MULT_ALPHA_P_MMD_NONE (0 << 8)
228 #define VI6_RPF_MULT_ALPHA_RATIO_MASK (0xff << 0)
229 #define VI6_RPF_MULT_ALPHA_RATIO_SHIFT 0
235 #define VI6_WPF_OFFSET 0x100
237 #define VI6_WPF_SRCRPF 0x1000
238 #define VI6_WPF_SRCRPF_VIRACT_DIS (0 << 28)
242 #define VI6_WPF_SRCRPF_VIRACT2_DIS (0 << 24)
246 #define VI6_WPF_SRCRPF_RPF_ACT_DIS(n) (0 << ((n) * 2))
251 #define VI6_WPF_HSZCLIP 0x1004
252 #define VI6_WPF_VSZCLIP 0x1008
254 #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16)
256 #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0)
257 #define VI6_WPF_SZCLIP_SIZE_SHIFT 0
259 #define VI6_WPF_OUTFMT 0x100c
260 #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24)
268 #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12)
271 #define VI6_WPF_OUTFMT_WRTM_BT601 (0 << 9)
277 #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0)
278 #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0
280 #define VI6_WPF_DSWAP 0x1010
284 #define VI6_WPF_DSWAP_P_BTS BIT(0)
286 #define VI6_WPF_RNDCTRL 0x1014
288 #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24)
292 #define VI6_WPF_RNDCTRL_ATHRESH_MASK (0xff << 16)
294 #define VI6_WPF_RNDCTRL_CLMD_FULL (0 << 12)
299 #define VI6_WPF_ROT_CTRL 0x1018
301 #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0)
302 #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0
304 #define VI6_WPF_DSTM_STRIDE_Y 0x101c
305 #define VI6_WPF_DSTM_STRIDE_C 0x1020
306 #define VI6_WPF_DSTM_ADDR_Y 0x1024
307 #define VI6_WPF_DSTM_ADDR_C0 0x1028
308 #define VI6_WPF_DSTM_ADDR_C1 0x102c
310 #define VI6_WPF_WRBCK_CTRL(n) (0x1034 + (n) * 0x100)
311 #define VI6_WPF_WRBCK_CTRL_WBMD BIT(0)
317 #define VI6_UIF_OFFSET 0x100
319 #define VI6_UIF_DISCOM_DOCMCR 0x1c00
321 #define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0)
323 #define VI6_UIF_DISCOM_DOCMSTR 0x1c04
325 #define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0)
327 #define VI6_UIF_DISCOM_DOCMCLSTR 0x1c08
329 #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0)
331 #define VI6_UIF_DISCOM_DOCMIENR 0x1c0c
333 #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0)
335 #define VI6_UIF_DISCOM_DOCMMDR 0x1c10
338 #define VI6_UIF_DISCOM_DOCMPMR 0x1c14
342 #define VI6_UIF_DISCOM_DOCMPMR_SEL(n) ((n) << 0)
344 #define VI6_UIF_DISCOM_DOCMECRCR 0x1c18
345 #define VI6_UIF_DISCOM_DOCMCCRCR 0x1c1c
346 #define VI6_UIF_DISCOM_DOCMSPXR 0x1c20
347 #define VI6_UIF_DISCOM_DOCMSPYR 0x1c24
348 #define VI6_UIF_DISCOM_DOCMSZXR 0x1c28
349 #define VI6_UIF_DISCOM_DOCMSZYR 0x1c2c
355 #define VI6_DPR_RPF_ROUTE(n) (0x2000 + (n) * 4)
357 #define VI6_DPR_WPF_FPORCH(n) (0x2014 + (n) * 4)
360 #define VI6_DPR_SRU_ROUTE 0x2024
361 #define VI6_DPR_UDS_ROUTE(n) (0x2028 + (n) * 4)
362 #define VI6_DPR_LUT_ROUTE 0x203c
363 #define VI6_DPR_CLU_ROUTE 0x2040
364 #define VI6_DPR_HST_ROUTE 0x2044
365 #define VI6_DPR_HSI_ROUTE 0x2048
366 #define VI6_DPR_BRU_ROUTE 0x204c
367 #define VI6_DPR_ILV_BRS_ROUTE 0x2050
369 #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16)
371 #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8)
373 #define VI6_DPR_ROUTE_RT_MASK (0x3f << 0)
374 #define VI6_DPR_ROUTE_RT_SHIFT 0
376 #define VI6_DPR_HGO_SMPPT 0x2054
377 #define VI6_DPR_HGT_SMPPT 0x2058
380 #define VI6_DPR_SMPPT_PT_MASK (0x3f << 0)
381 #define VI6_DPR_SMPPT_PT_SHIFT 0
383 #define VI6_DPR_UIF_ROUTE(n) (0x2074 + (n) * 4)
404 #define VI6_SRU_CTRL0 0x2200
405 #define VI6_SRU_CTRL0_PARAM0_MASK (0x1ff << 16)
407 #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8)
413 #define VI6_SRU_CTRL0_EN BIT(0)
415 #define VI6_SRU_CTRL1 0x2204
416 #define VI6_SRU_CTRL1_PARAM5 0x7ff
418 #define VI6_SRU_CTRL2 0x2208
421 #define VI6_SRU_CTRL2_PARAM8_SHIFT 0
427 #define VI6_UDS_OFFSET 0x100
429 #define VI6_UDS_CTRL 0x2300
443 #define VI6_UDS_SCALE 0x2304
444 #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28)
446 #define VI6_UDS_SCALE_HFRAC_MASK (0xfff << 16)
448 #define VI6_UDS_SCALE_VMANT_MASK (0xf << 12)
450 #define VI6_UDS_SCALE_VFRAC_MASK (0xfff << 0)
451 #define VI6_UDS_SCALE_VFRAC_SHIFT 0
453 #define VI6_UDS_ALPTH 0x2308
454 #define VI6_UDS_ALPTH_TH1_MASK (0xff << 8)
456 #define VI6_UDS_ALPTH_TH0_MASK (0xff << 0)
457 #define VI6_UDS_ALPTH_TH0_SHIFT 0
459 #define VI6_UDS_ALPVAL 0x230c
460 #define VI6_UDS_ALPVAL_VAL2_MASK (0xff << 16)
462 #define VI6_UDS_ALPVAL_VAL1_MASK (0xff << 8)
464 #define VI6_UDS_ALPVAL_VAL0_MASK (0xff << 0)
465 #define VI6_UDS_ALPVAL_VAL0_SHIFT 0
467 #define VI6_UDS_PASS_BWIDTH 0x2310
468 #define VI6_UDS_PASS_BWIDTH_H_MASK (0x7f << 16)
470 #define VI6_UDS_PASS_BWIDTH_V_MASK (0x7f << 0)
471 #define VI6_UDS_PASS_BWIDTH_V_SHIFT 0
473 #define VI6_UDS_HPHASE 0x2314
474 #define VI6_UDS_HPHASE_HSTP_MASK (0xfff << 16)
476 #define VI6_UDS_HPHASE_HEDP_MASK (0xfff << 0)
477 #define VI6_UDS_HPHASE_HEDP_SHIFT 0
479 #define VI6_UDS_IPC 0x2318
481 #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0)
482 #define VI6_UDS_IPC_VEDP_SHIFT 0
484 #define VI6_UDS_HSZCLIP 0x231c
486 #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16)
488 #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK (0x1fff << 0)
489 #define VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT 0
491 #define VI6_UDS_CLIP_SIZE 0x2324
492 #define VI6_UDS_CLIP_SIZE_HSIZE_MASK (0x1fff << 16)
494 #define VI6_UDS_CLIP_SIZE_VSIZE_MASK (0x1fff << 0)
495 #define VI6_UDS_CLIP_SIZE_VSIZE_SHIFT 0
497 #define VI6_UDS_FILL_COLOR 0x2328
498 #define VI6_UDS_FILL_COLOR_RFILC_MASK (0xff << 16)
500 #define VI6_UDS_FILL_COLOR_GFILC_MASK (0xff << 8)
502 #define VI6_UDS_FILL_COLOR_BFILC_MASK (0xff << 0)
503 #define VI6_UDS_FILL_COLOR_BFILC_SHIFT 0
509 #define VI6_LUT_CTRL 0x2800
510 #define VI6_LUT_CTRL_EN BIT(0)
516 #define VI6_CLU_CTRL 0x2900
525 #define VI6_CLU_CTRL_EN BIT(0)
531 #define VI6_HST_CTRL 0x2a00
532 #define VI6_HST_CTRL_EN BIT(0)
538 #define VI6_HSI_CTRL 0x2b00
539 #define VI6_HSI_CTRL_EN BIT(0)
545 #define VI6_ROP_NOP 0
562 #define VI6_BRU_BASE 0x2c00
563 #define VI6_BRS_BASE 0x3900
565 #define VI6_BRU_INCTRL 0x0000
568 #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4))
577 #define VI6_BRU_VIRRPF_SIZE 0x0004
578 #define VI6_BRU_VIRRPF_SIZE_HSIZE_MASK (0x1fff << 16)
580 #define VI6_BRU_VIRRPF_SIZE_VSIZE_MASK (0x1fff << 0)
581 #define VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT 0
583 #define VI6_BRU_VIRRPF_LOC 0x0008
584 #define VI6_BRU_VIRRPF_LOC_HCOORD_MASK (0x1fff << 16)
586 #define VI6_BRU_VIRRPF_LOC_VCOORD_MASK (0x1fff << 0)
587 #define VI6_BRU_VIRRPF_LOC_VCOORD_SHIFT 0
589 #define VI6_BRU_VIRRPF_COL 0x000c
590 #define VI6_BRU_VIRRPF_COL_A_MASK (0xff << 24)
592 #define VI6_BRU_VIRRPF_COL_RCR_MASK (0xff << 16)
594 #define VI6_BRU_VIRRPF_COL_GY_MASK (0xff << 8)
596 #define VI6_BRU_VIRRPF_COL_BCB_MASK (0xff << 0)
597 #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0
599 #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4))
608 #define VI6_BRU_CTRL_CROP_MASK (0xf << 4)
609 #define VI6_BRU_CTRL_AROP(rop) ((rop) << 0)
610 #define VI6_BRU_CTRL_AROP_MASK (0xf << 0)
612 #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4))
614 #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28)
620 #define VI6_BRU_BLD_CCMDY_DST_A (0 << 24)
628 #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20)
634 #define VI6_BRU_BLD_ACMDY_DST_A (0 << 16)
640 #define VI6_BRU_BLD_COEFX_MASK (0xff << 8)
642 #define VI6_BRU_BLD_COEFY_MASK (0xff << 0)
643 #define VI6_BRU_BLD_COEFY_SHIFT 0
645 #define VI6_BRU_ROP 0x0030 /* Only available on BRU */
650 #define VI6_BRU_ROP_CROP_MASK (0xf << 4)
651 #define VI6_BRU_ROP_AROP(rop) ((rop) << 0)
652 #define VI6_BRU_ROP_AROP_MASK (0xf << 0)
658 #define VI6_HGO_OFFSET 0x3000
660 #define VI6_HGO_OFFSET_VOFFSET_SHIFT 0
661 #define VI6_HGO_SIZE 0x3004
663 #define VI6_HGO_SIZE_VSIZE_SHIFT 0
664 #define VI6_HGO_MODE 0x3008
671 #define VI6_HGO_MODE_VRATIO_SHIFT 0
672 #define VI6_HGO_LB_TH 0x300c
673 #define VI6_HGO_LBn_H(n) (0x3010 + (n) * 8)
674 #define VI6_HGO_LBn_V(n) (0x3014 + (n) * 8)
675 #define VI6_HGO_R_HISTO(n) (0x3030 + (n) * 4)
676 #define VI6_HGO_R_MAXMIN 0x3130
677 #define VI6_HGO_R_SUM 0x3134
678 #define VI6_HGO_R_LB_DET 0x3138
679 #define VI6_HGO_G_HISTO(n) (0x3140 + (n) * 4)
680 #define VI6_HGO_G_MAXMIN 0x3240
681 #define VI6_HGO_G_SUM 0x3244
682 #define VI6_HGO_G_LB_DET 0x3248
683 #define VI6_HGO_B_HISTO(n) (0x3250 + (n) * 4)
684 #define VI6_HGO_B_MAXMIN 0x3350
685 #define VI6_HGO_B_SUM 0x3354
686 #define VI6_HGO_B_LB_DET 0x3358
687 #define VI6_HGO_EXT_HIST_ADDR 0x335c
688 #define VI6_HGO_EXT_HIST_DATA 0x3360
689 #define VI6_HGO_REGRST 0x33fc
690 #define VI6_HGO_REGRST_RCLEA BIT(0)
696 #define VI6_HGT_OFFSET 0x3400
698 #define VI6_HGT_OFFSET_VOFFSET_SHIFT 0
699 #define VI6_HGT_SIZE 0x3404
701 #define VI6_HGT_SIZE_VSIZE_SHIFT 0
702 #define VI6_HGT_MODE 0x3408
704 #define VI6_HGT_MODE_VRATIO_SHIFT 0
705 #define VI6_HGT_HUE_AREA(n) (0x340c + (n) * 4)
707 #define VI6_HGT_HUE_AREA_UPPER_SHIFT 0
708 #define VI6_HGT_LB_TH 0x3424
709 #define VI6_HGT_LBn_H(n) (0x3428 + (n) * 8)
710 #define VI6_HGT_LBn_V(n) (0x342c + (n) * 8)
711 #define VI6_HGT_HISTO(m, n) (0x3450 + (m) * 128 + (n) * 4)
712 #define VI6_HGT_MAXMIN 0x3750
713 #define VI6_HGT_SUM 0x3754
714 #define VI6_HGT_LB_DET 0x3758
715 #define VI6_HGT_REGRST 0x37fc
716 #define VI6_HGT_REGRST_RCLEA BIT(0)
722 #define VI6_LIF_OFFSET (-0x100)
724 #define VI6_LIF_CTRL 0x3b00
725 #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16)
729 #define VI6_LIF_CTRL_LIF_EN BIT(0)
731 #define VI6_LIF_CSBTH 0x3b04
732 #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16)
734 #define VI6_LIF_CSBTH_LBTH_MASK (0x7ff << 0)
735 #define VI6_LIF_CSBTH_LBTH_SHIFT 0
737 #define VI6_LIF_LBA 0x3b0c
739 #define VI6_LIF_LBA_LBA1_MASK (0xfff << 16)
746 #define VI6_SECURITY_CTRL0 0x3d00
747 #define VI6_SECURITY_CTRL1 0x3d04
753 #define VI6_IP_VERSION 0x3f00
754 #define VI6_IP_VERSION_MASK (0xffff << 0)
755 #define VI6_IP_VERSION_MODEL_MASK (0xff << 8)
756 #define VI6_IP_VERSION_MODEL_VSPS_H2 (0x09 << 8)
757 #define VI6_IP_VERSION_MODEL_VSPR_H2 (0x0a << 8)
758 #define VI6_IP_VERSION_MODEL_VSPD_GEN2 (0x0b << 8)
759 #define VI6_IP_VERSION_MODEL_VSPS_M2 (0x0c << 8)
760 #define VI6_IP_VERSION_MODEL_VSPS_V2H (0x12 << 8)
761 #define VI6_IP_VERSION_MODEL_VSPD_V2H (0x13 << 8)
762 #define VI6_IP_VERSION_MODEL_VSPI_GEN3 (0x14 << 8)
763 #define VI6_IP_VERSION_MODEL_VSPBD_GEN3 (0x15 << 8)
764 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3 (0x16 << 8)
765 #define VI6_IP_VERSION_MODEL_VSPD_GEN3 (0x17 << 8)
766 #define VI6_IP_VERSION_MODEL_VSPD_V3 (0x18 << 8)
767 #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8)
768 #define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8)
769 #define VI6_IP_VERSION_MODEL_VSPD_V3U (0x1c << 8)
770 /* RZ/G2L SoCs have no version register, So use 0x80 as the model version */
771 #define VI6_IP_VERSION_MODEL_VSPD_RZG2L (0x80 << 8)
773 #define VI6_IP_VERSION_SOC_MASK (0xff << 0)
774 #define VI6_IP_VERSION_SOC_H2 (0x01 << 0)
775 #define VI6_IP_VERSION_SOC_V2H (0x01 << 0)
776 #define VI6_IP_VERSION_SOC_V3M (0x01 << 0)
777 #define VI6_IP_VERSION_SOC_M2 (0x02 << 0)
778 #define VI6_IP_VERSION_SOC_M3W (0x02 << 0)
779 #define VI6_IP_VERSION_SOC_V3H (0x02 << 0)
780 #define VI6_IP_VERSION_SOC_H3 (0x03 << 0)
781 #define VI6_IP_VERSION_SOC_D3 (0x04 << 0)
782 #define VI6_IP_VERSION_SOC_M3N (0x04 << 0)
783 #define VI6_IP_VERSION_SOC_E3 (0x04 << 0)
784 #define VI6_IP_VERSION_SOC_V3U (0x05 << 0)
785 /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */
786 #define VI6_IP_VERSION_SOC_RZG2L (0x80 << 0)
788 #define VI6_IP_VERSION_VSP_SW (0xfffe << 16) /* SW VSP version */
794 #define VI6_CLUT_TABLE 0x4000
800 #define VI6_LUT_TABLE 0x7000
806 #define VI6_CLU_ADDR 0x7400
807 #define VI6_CLU_DATA 0x7404
813 #define VI6_FMT_RGB_332 0x00
814 #define VI6_FMT_XRGB_4444 0x01
815 #define VI6_FMT_RGBX_4444 0x02
816 #define VI6_FMT_XRGB_1555 0x04
817 #define VI6_FMT_RGBX_5551 0x05
818 #define VI6_FMT_RGB_565 0x06
819 #define VI6_FMT_AXRGB_86666 0x07
820 #define VI6_FMT_RGBXA_66668 0x08
821 #define VI6_FMT_XRGBA_66668 0x09
822 #define VI6_FMT_ARGBX_86666 0x0a
823 #define VI6_FMT_AXRXGXB_8262626 0x0b
824 #define VI6_FMT_XRXGXBA_2626268 0x0c
825 #define VI6_FMT_ARXGXBX_8626262 0x0d
826 #define VI6_FMT_RXGXBXA_6262628 0x0e
827 #define VI6_FMT_XRGB_6666 0x0f
828 #define VI6_FMT_RGBX_6666 0x10
829 #define VI6_FMT_XRXGXB_262626 0x11
830 #define VI6_FMT_RXGXBX_626262 0x12
831 #define VI6_FMT_ARGB_8888 0x13
832 #define VI6_FMT_RGBA_8888 0x14
833 #define VI6_FMT_RGB_888 0x15
834 #define VI6_FMT_XRGXGB_763763 0x16
835 #define VI6_FMT_XXRGB_86666 0x17
836 #define VI6_FMT_BGR_888 0x18
837 #define VI6_FMT_ARGB_4444 0x19
838 #define VI6_FMT_RGBA_4444 0x1a
839 #define VI6_FMT_ARGB_1555 0x1b
840 #define VI6_FMT_RGBA_5551 0x1c
841 #define VI6_FMT_ABGR_4444 0x1d
842 #define VI6_FMT_BGRA_4444 0x1e
843 #define VI6_FMT_ABGR_1555 0x1f
844 #define VI6_FMT_BGRA_5551 0x20
845 #define VI6_FMT_XBXGXR_262626 0x21
846 #define VI6_FMT_ABGR_8888 0x22
847 #define VI6_FMT_XXRGB_88565 0x23
849 #define VI6_FMT_Y_UV_444 0x40
850 #define VI6_FMT_Y_UV_422 0x41
851 #define VI6_FMT_Y_UV_420 0x42
852 #define VI6_FMT_YUV_444 0x46
853 #define VI6_FMT_YUYV_422 0x47
854 #define VI6_FMT_YYUV_422 0x48
855 #define VI6_FMT_YUV_420 0x49
856 #define VI6_FMT_Y_U_V_444 0x4a
857 #define VI6_FMT_Y_U_V_422 0x4b
858 #define VI6_FMT_Y_U_V_420 0x4c