Lines Matching full:vin
3 * Driver for Renesas R-Car VIN
19 #include "rcar-vin.h"
25 /* Register offsets for R-Car VIN */
78 /* Register bit fields for R-Car VIN */
152 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset) in rvin_write() argument
154 iowrite32(value, vin->base + offset); in rvin_write()
157 static u32 rvin_read(struct rvin_dev *vin, u32 offset) in rvin_read() argument
159 return ioread32(vin->base + offset); in rvin_read()
484 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs) in rvin_set_coeff() argument
505 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
506 rvin_write(vin, p_set->coeff_set[1], VNC1B_REG); in rvin_set_coeff()
507 rvin_write(vin, p_set->coeff_set[2], VNC1C_REG); in rvin_set_coeff()
509 rvin_write(vin, p_set->coeff_set[3], VNC2A_REG); in rvin_set_coeff()
510 rvin_write(vin, p_set->coeff_set[4], VNC2B_REG); in rvin_set_coeff()
511 rvin_write(vin, p_set->coeff_set[5], VNC2C_REG); in rvin_set_coeff()
513 rvin_write(vin, p_set->coeff_set[6], VNC3A_REG); in rvin_set_coeff()
514 rvin_write(vin, p_set->coeff_set[7], VNC3B_REG); in rvin_set_coeff()
515 rvin_write(vin, p_set->coeff_set[8], VNC3C_REG); in rvin_set_coeff()
517 rvin_write(vin, p_set->coeff_set[9], VNC4A_REG); in rvin_set_coeff()
518 rvin_write(vin, p_set->coeff_set[10], VNC4B_REG); in rvin_set_coeff()
519 rvin_write(vin, p_set->coeff_set[11], VNC4C_REG); in rvin_set_coeff()
521 rvin_write(vin, p_set->coeff_set[12], VNC5A_REG); in rvin_set_coeff()
522 rvin_write(vin, p_set->coeff_set[13], VNC5B_REG); in rvin_set_coeff()
523 rvin_write(vin, p_set->coeff_set[14], VNC5C_REG); in rvin_set_coeff()
525 rvin_write(vin, p_set->coeff_set[15], VNC6A_REG); in rvin_set_coeff()
526 rvin_write(vin, p_set->coeff_set[16], VNC6B_REG); in rvin_set_coeff()
527 rvin_write(vin, p_set->coeff_set[17], VNC6C_REG); in rvin_set_coeff()
529 rvin_write(vin, p_set->coeff_set[18], VNC7A_REG); in rvin_set_coeff()
530 rvin_write(vin, p_set->coeff_set[19], VNC7B_REG); in rvin_set_coeff()
531 rvin_write(vin, p_set->coeff_set[20], VNC7C_REG); in rvin_set_coeff()
533 rvin_write(vin, p_set->coeff_set[21], VNC8A_REG); in rvin_set_coeff()
534 rvin_write(vin, p_set->coeff_set[22], VNC8B_REG); in rvin_set_coeff()
535 rvin_write(vin, p_set->coeff_set[23], VNC8C_REG); in rvin_set_coeff()
538 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin) in rvin_crop_scale_comp_gen2() argument
544 crop_height = vin->crop.height; in rvin_crop_scale_comp_gen2()
545 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_crop_scale_comp_gen2()
549 if (crop_height != vin->compose.height) in rvin_crop_scale_comp_gen2()
550 ys = (4096 * crop_height) / vin->compose.height; in rvin_crop_scale_comp_gen2()
551 rvin_write(vin, ys, VNYS_REG); in rvin_crop_scale_comp_gen2()
554 if (vin->crop.width != vin->compose.width) in rvin_crop_scale_comp_gen2()
555 xs = (4096 * vin->crop.width) / vin->compose.width; in rvin_crop_scale_comp_gen2()
561 rvin_write(vin, xs, VNXS_REG); in rvin_crop_scale_comp_gen2()
567 rvin_set_coeff(vin, xs); in rvin_crop_scale_comp_gen2()
570 rvin_write(vin, 0, VNSPPOC_REG); in rvin_crop_scale_comp_gen2()
571 rvin_write(vin, 0, VNSLPOC_REG); in rvin_crop_scale_comp_gen2()
572 rvin_write(vin, vin->format.width - 1, VNEPPOC_REG); in rvin_crop_scale_comp_gen2()
574 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_crop_scale_comp_gen2()
575 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG); in rvin_crop_scale_comp_gen2()
577 rvin_write(vin, vin->format.height - 1, VNELPOC_REG); in rvin_crop_scale_comp_gen2()
579 vin_dbg(vin, in rvin_crop_scale_comp_gen2()
581 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_crop_scale_comp_gen2()
582 vin->crop.top, ys, xs, vin->format.width, vin->format.height, in rvin_crop_scale_comp_gen2()
586 void rvin_crop_scale_comp(struct rvin_dev *vin) in rvin_crop_scale_comp() argument
592 rvin_write(vin, vin->crop.left, VNSPPRC_REG); in rvin_crop_scale_comp()
593 rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG); in rvin_crop_scale_comp()
594 rvin_write(vin, vin->crop.top, VNSLPRC_REG); in rvin_crop_scale_comp()
595 rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG); in rvin_crop_scale_comp()
598 if (vin->info->model != RCAR_GEN3) in rvin_crop_scale_comp()
599 rvin_crop_scale_comp_gen2(vin); in rvin_crop_scale_comp()
601 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_crop_scale_comp()
602 stride = vin->format.bytesperline / fmt->bpp; in rvin_crop_scale_comp()
607 switch (vin->format.pixelformat) { in rvin_crop_scale_comp()
619 rvin_write(vin, stride, VNIS_REG); in rvin_crop_scale_comp()
626 static int rvin_setup(struct rvin_dev *vin) in rvin_setup() argument
631 switch (vin->format.field) { in rvin_setup()
642 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60) in rvin_setup()
668 switch (vin->mbus_code) { in rvin_setup()
680 if (!vin->is_csi && in rvin_setup()
681 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
693 if (!vin->is_csi && in rvin_setup()
694 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
713 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
719 if (vin->is_csi) { in rvin_setup()
720 vin_err(vin, "Invalid setting in MIPI CSI2\n"); in rvin_setup()
725 if (!vin->is_csi) { in rvin_setup()
726 vin_err(vin, "Invalid setting in Digital Pins\n"); in rvin_setup()
736 if (vin->info->model == RCAR_GEN3) in rvin_setup()
741 if (!vin->is_csi) { in rvin_setup()
743 if (!(vin->parallel.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) in rvin_setup()
747 if (!(vin->parallel.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) in rvin_setup()
751 if (vin->parallel.bus.flags & V4L2_MBUS_DATA_ENABLE_LOW) in rvin_setup()
754 switch (vin->mbus_code) { in rvin_setup()
756 if (vin->parallel.bus.bus_width == 8 && in rvin_setup()
757 vin->parallel.bus.data_shift == 8) in rvin_setup()
768 switch (vin->format.pixelformat) { in rvin_setup()
771 rvin_write(vin, in rvin_setup()
772 ALIGN(vin->format.bytesperline * vin->format.height, in rvin_setup()
774 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ? in rvin_setup()
797 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
800 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB; in rvin_setup()
817 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
818 vin->format.pixelformat); in rvin_setup()
825 if (!vin->info->use_isp) { in rvin_setup()
830 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
832 if (vin->is_csi) in rvin_setup()
843 rvin_write(vin, interrupts, VNINTS_REG); in rvin_setup()
845 rvin_write(vin, interrupts, VNIE_REG); in rvin_setup()
847 rvin_write(vin, dmr, VNDMR_REG); in rvin_setup()
848 rvin_write(vin, dmr2, VNDMR2_REG); in rvin_setup()
851 rvin_write(vin, vnmc | VNMC_ME, VNMC_REG); in rvin_setup()
856 static void rvin_disable_interrupts(struct rvin_dev *vin) in rvin_disable_interrupts() argument
858 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
861 static u32 rvin_get_interrupt_status(struct rvin_dev *vin) in rvin_get_interrupt_status() argument
863 return rvin_read(vin, VNINTS_REG); in rvin_get_interrupt_status()
866 static void rvin_ack_interrupt(struct rvin_dev *vin) in rvin_ack_interrupt() argument
868 rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG); in rvin_ack_interrupt()
871 static bool rvin_capture_active(struct rvin_dev *vin) in rvin_capture_active() argument
873 return rvin_read(vin, VNMS_REG) & VNMS_CA; in rvin_capture_active()
876 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms) in rvin_get_active_field() argument
878 if (vin->format.field == V4L2_FIELD_ALTERNATE) { in rvin_get_active_field()
885 return vin->format.field; in rvin_get_active_field()
888 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr) in rvin_set_slot_addr() argument
894 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_set_slot_addr()
900 offsetx = vin->compose.left * fmt->bpp; in rvin_set_slot_addr()
901 offsety = vin->compose.top * vin->format.bytesperline; in rvin_set_slot_addr()
911 rvin_write(vin, offset, VNMB_REG(slot)); in rvin_set_slot_addr()
920 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot) in rvin_fill_hw_slot() argument
928 if (WARN_ON(vin->buf_hw[slot].buffer)) in rvin_fill_hw_slot()
933 if (vin->buf_hw[prev].type == HALF_TOP) { in rvin_fill_hw_slot()
934 vbuf = vin->buf_hw[prev].buffer; in rvin_fill_hw_slot()
935 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
936 vin->buf_hw[slot].type = HALF_BOTTOM; in rvin_fill_hw_slot()
937 switch (vin->format.pixelformat) { in rvin_fill_hw_slot()
940 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
941 vin->format.sizeimage / 4; in rvin_fill_hw_slot()
944 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
945 vin->format.sizeimage / 2; in rvin_fill_hw_slot()
948 } else if ((vin->state != STOPPED && vin->state != RUNNING) || in rvin_fill_hw_slot()
949 list_empty(&vin->buf_list)) { in rvin_fill_hw_slot()
950 vin->buf_hw[slot].buffer = NULL; in rvin_fill_hw_slot()
951 vin->buf_hw[slot].type = FULL; in rvin_fill_hw_slot()
952 phys_addr = vin->scratch_phys; in rvin_fill_hw_slot()
955 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list); in rvin_fill_hw_slot()
958 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
960 vin->buf_hw[slot].type = in rvin_fill_hw_slot()
961 V4L2_FIELD_IS_SEQUENTIAL(vin->format.field) ? in rvin_fill_hw_slot()
968 vin_dbg(vin, "Filling HW slot: %d type: %d buffer: %p\n", in rvin_fill_hw_slot()
969 slot, vin->buf_hw[slot].type, vin->buf_hw[slot].buffer); in rvin_fill_hw_slot()
971 vin->buf_hw[slot].phys = phys_addr; in rvin_fill_hw_slot()
972 rvin_set_slot_addr(vin, slot, phys_addr); in rvin_fill_hw_slot()
975 static int rvin_capture_start(struct rvin_dev *vin) in rvin_capture_start() argument
980 vin->buf_hw[slot].buffer = NULL; in rvin_capture_start()
981 vin->buf_hw[slot].type = FULL; in rvin_capture_start()
985 rvin_fill_hw_slot(vin, slot); in rvin_capture_start()
987 rvin_crop_scale_comp(vin); in rvin_capture_start()
989 ret = rvin_setup(vin); in rvin_capture_start()
993 vin_dbg(vin, "Starting to capture\n"); in rvin_capture_start()
996 rvin_write(vin, VNFC_C_FRAME, VNFC_REG); in rvin_capture_start()
998 vin->state = STARTING; in rvin_capture_start()
1003 static void rvin_capture_stop(struct rvin_dev *vin) in rvin_capture_stop() argument
1006 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
1009 rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG); in rvin_capture_stop()
1021 struct rvin_dev *vin = data; in rvin_irq() local
1027 spin_lock_irqsave(&vin->qlock, flags); in rvin_irq()
1029 int_status = rvin_get_interrupt_status(vin); in rvin_irq()
1033 rvin_ack_interrupt(vin); in rvin_irq()
1041 if (vin->state == STOPPED) { in rvin_irq()
1042 vin_dbg(vin, "IRQ while state stopped\n"); in rvin_irq()
1047 vnms = rvin_read(vin, VNMS_REG); in rvin_irq()
1054 if (vin->state == STARTING) { in rvin_irq()
1056 vin_dbg(vin, "Starting sync slot: %d\n", slot); in rvin_irq()
1060 vin_dbg(vin, "Capture start synced!\n"); in rvin_irq()
1061 vin->state = RUNNING; in rvin_irq()
1065 if (vin->buf_hw[slot].buffer) { in rvin_irq()
1070 if (vin->buf_hw[slot].type == HALF_TOP) { in rvin_irq()
1071 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1072 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1076 vin->buf_hw[slot].buffer->field = in rvin_irq()
1077 rvin_get_active_field(vin, vnms); in rvin_irq()
1078 vin->buf_hw[slot].buffer->sequence = vin->sequence; in rvin_irq()
1079 vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns(); in rvin_irq()
1080 vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf, in rvin_irq()
1082 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1085 vin_dbg(vin, "Dropping frame %u\n", vin->sequence); in rvin_irq()
1088 vin->sequence++; in rvin_irq()
1091 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1093 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_irq()
1098 static void return_unused_buffers(struct rvin_dev *vin, in return_unused_buffers() argument
1104 spin_lock_irqsave(&vin->qlock, flags); in return_unused_buffers()
1106 list_for_each_entry_safe(buf, node, &vin->buf_list, list) { in return_unused_buffers()
1111 spin_unlock_irqrestore(&vin->qlock, flags); in return_unused_buffers()
1119 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_queue_setup() local
1123 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1126 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1133 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_prepare() local
1134 unsigned long size = vin->format.sizeimage; in rvin_buffer_prepare()
1137 vin_err(vin, "buffer too small (%lu < %lu)\n", in rvin_buffer_prepare()
1150 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_queue() local
1153 spin_lock_irqsave(&vin->qlock, flags); in rvin_buffer_queue()
1155 list_add_tail(to_buf_list(vbuf), &vin->buf_list); in rvin_buffer_queue()
1157 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_buffer_queue()
1160 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd, in rvin_mc_validate_format() argument
1179 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8) in rvin_mc_validate_format()
1183 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8) in rvin_mc_validate_format()
1187 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8) in rvin_mc_validate_format()
1191 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8) in rvin_mc_validate_format()
1195 if (vin->format.pixelformat != V4L2_PIX_FMT_GREY) in rvin_mc_validate_format()
1201 vin->mbus_code = fmt.format.code; in rvin_mc_validate_format()
1215 switch (vin->format.field) { in rvin_mc_validate_format()
1226 /* Use VIN hardware to combine the two fields */ in rvin_mc_validate_format()
1237 if (fmt.format.width != vin->format.width || in rvin_mc_validate_format()
1238 fmt.format.height != vin->format.height || in rvin_mc_validate_format()
1239 fmt.format.code != vin->mbus_code) in rvin_mc_validate_format()
1245 static int rvin_set_stream(struct rvin_dev *vin, int on) in rvin_set_stream() argument
1252 if (!vin->info->use_mc) { in rvin_set_stream()
1253 ret = v4l2_subdev_call(vin->parallel.subdev, video, s_stream, in rvin_set_stream()
1259 pad = media_pad_remote_pad_first(&vin->pad); in rvin_set_stream()
1266 video_device_pipeline_stop(&vin->vdev); in rvin_set_stream()
1270 ret = rvin_mc_validate_format(vin, sd, pad); in rvin_set_stream()
1274 ret = video_device_pipeline_alloc_start(&vin->vdev); in rvin_set_stream()
1282 video_device_pipeline_stop(&vin->vdev); in rvin_set_stream()
1287 int rvin_start_streaming(struct rvin_dev *vin) in rvin_start_streaming() argument
1292 ret = rvin_set_stream(vin, 1); in rvin_start_streaming()
1296 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1298 vin->sequence = 0; in rvin_start_streaming()
1300 ret = rvin_capture_start(vin); in rvin_start_streaming()
1302 rvin_set_stream(vin, 0); in rvin_start_streaming()
1304 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1311 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_start_streaming_vq() local
1315 vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage, in rvin_start_streaming_vq()
1316 &vin->scratch_phys, GFP_KERNEL); in rvin_start_streaming_vq()
1317 if (!vin->scratch) in rvin_start_streaming_vq()
1320 ret = rvin_start_streaming(vin); in rvin_start_streaming_vq()
1326 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_start_streaming_vq()
1327 vin->scratch_phys); in rvin_start_streaming_vq()
1329 return_unused_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming_vq()
1334 void rvin_stop_streaming(struct rvin_dev *vin) in rvin_stop_streaming() argument
1340 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1342 if (vin->state == STOPPED) { in rvin_stop_streaming()
1343 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1347 vin->state = STOPPING; in rvin_stop_streaming()
1354 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1360 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1362 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1369 rvin_capture_stop(vin); in rvin_stop_streaming()
1372 if (!rvin_capture_active(vin)) { in rvin_stop_streaming()
1373 vin->state = STOPPED; in rvin_stop_streaming()
1377 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1379 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1382 if (!buffersFreed || vin->state != STOPPED) { in rvin_stop_streaming()
1388 vin_err(vin, "Failed stop HW, something is seriously broken\n"); in rvin_stop_streaming()
1389 vin->state = STOPPED; in rvin_stop_streaming()
1392 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1396 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming()
1398 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1399 vb2_buffer_done(&vin->buf_hw[i].buffer->vb2_buf, in rvin_stop_streaming()
1404 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1407 rvin_disable_interrupts(vin); in rvin_stop_streaming()
1412 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_stop_streaming_vq() local
1414 rvin_stop_streaming(vin); in rvin_stop_streaming_vq()
1417 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_stop_streaming_vq()
1418 vin->scratch_phys); in rvin_stop_streaming_vq()
1420 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming_vq()
1433 void rvin_dma_unregister(struct rvin_dev *vin) in rvin_dma_unregister() argument
1435 mutex_destroy(&vin->lock); in rvin_dma_unregister()
1437 v4l2_device_unregister(&vin->v4l2_dev); in rvin_dma_unregister()
1440 int rvin_dma_register(struct rvin_dev *vin, int irq) in rvin_dma_register() argument
1442 struct vb2_queue *q = &vin->queue; in rvin_dma_register()
1446 ret = v4l2_device_register(vin->dev, &vin->v4l2_dev); in rvin_dma_register()
1450 mutex_init(&vin->lock); in rvin_dma_register()
1451 INIT_LIST_HEAD(&vin->buf_list); in rvin_dma_register()
1453 spin_lock_init(&vin->qlock); in rvin_dma_register()
1455 vin->state = STOPPED; in rvin_dma_register()
1458 vin->buf_hw[i].buffer = NULL; in rvin_dma_register()
1463 q->lock = &vin->lock; in rvin_dma_register()
1464 q->drv_priv = vin; in rvin_dma_register()
1470 q->dev = vin->dev; in rvin_dma_register()
1474 vin_err(vin, "failed to initialize VB2 queue\n"); in rvin_dma_register()
1479 ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED, in rvin_dma_register()
1480 KBUILD_MODNAME, vin); in rvin_dma_register()
1482 vin_err(vin, "failed to request irq\n"); in rvin_dma_register()
1488 rvin_dma_unregister(vin); in rvin_dma_register()
1499 * as it's only possible to do so when no VIN in the group is
1502 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) in rvin_set_channel_routing() argument
1509 ret = pm_runtime_resume_and_get(vin->dev); in rvin_set_channel_routing()
1514 vnmc = rvin_read(vin, VNMC_REG); in rvin_set_channel_routing()
1515 rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG); in rvin_set_channel_routing()
1523 for (route = vin->info->routes; route->chsel; route++) { in rvin_set_channel_routing()
1535 rvin_write(vin, ifmd, VNCSI_IFMD_REG); in rvin_set_channel_routing()
1538 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1540 vin->chsel = chsel; in rvin_set_channel_routing()
1543 rvin_write(vin, vnmc, VNMC_REG); in rvin_set_channel_routing()
1545 pm_runtime_put(vin->dev); in rvin_set_channel_routing()
1550 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha) in rvin_set_alpha() argument
1555 spin_lock_irqsave(&vin->qlock, flags); in rvin_set_alpha()
1557 vin->alpha = alpha; in rvin_set_alpha()
1559 if (vin->state == STOPPED) in rvin_set_alpha()
1562 switch (vin->format.pixelformat) { in rvin_set_alpha()
1564 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT; in rvin_set_alpha()
1565 if (vin->alpha) in rvin_set_alpha()
1569 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK; in rvin_set_alpha()
1570 dmr |= VNDMR_A8BIT(vin->alpha); in rvin_set_alpha()
1576 rvin_write(vin, dmr, VNDMR_REG); in rvin_set_alpha()
1578 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_set_alpha()