Lines Matching +full:0 +full:x3a00

26 #define VNMC_REG	0x00	/* Video n Main Control Register */
27 #define VNMS_REG 0x04 /* Video n Module Status Register */
28 #define VNFC_REG 0x08 /* Video n Frame Capture Register */
29 #define VNSLPRC_REG 0x0C /* Video n Start Line Pre-Clip Register */
30 #define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */
31 #define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */
32 #define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */
33 #define VNIS_REG 0x2C /* Video n Image Stride Register */
34 #define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
35 #define VNIE_REG 0x40 /* Video n Interrupt Enable Register */
36 #define VNINTS_REG 0x44 /* Video n Interrupt Status Register */
37 #define VNSI_REG 0x48 /* Video n Scanline Interrupt Register */
38 #define VNMTC_REG 0x4C /* Video n Memory Transfer Control Register */
39 #define VNDMR_REG 0x58 /* Video n Data Mode Register */
40 #define VNDMR2_REG 0x5C /* Video n Data Mode Register 2 */
41 #define VNUVAOF_REG 0x60 /* Video n UV Address Offset Register */
44 #define VNSLPOC_REG 0x1C /* Video n Start Line Post-Clip Register */
45 #define VNELPOC_REG 0x20 /* Video n End Line Post-Clip Register */
46 #define VNSPPOC_REG 0x24 /* Video n Start Pixel Post-Clip Register */
47 #define VNEPPOC_REG 0x28 /* Video n End Pixel Post-Clip Register */
48 #define VNYS_REG 0x50 /* Video n Y Scale Register */
49 #define VNXS_REG 0x54 /* Video n X Scale Register */
50 #define VNC1A_REG 0x80 /* Video n Coefficient Set C1A Register */
51 #define VNC1B_REG 0x84 /* Video n Coefficient Set C1B Register */
52 #define VNC1C_REG 0x88 /* Video n Coefficient Set C1C Register */
53 #define VNC2A_REG 0x90 /* Video n Coefficient Set C2A Register */
54 #define VNC2B_REG 0x94 /* Video n Coefficient Set C2B Register */
55 #define VNC2C_REG 0x98 /* Video n Coefficient Set C2C Register */
56 #define VNC3A_REG 0xA0 /* Video n Coefficient Set C3A Register */
57 #define VNC3B_REG 0xA4 /* Video n Coefficient Set C3B Register */
58 #define VNC3C_REG 0xA8 /* Video n Coefficient Set C3C Register */
59 #define VNC4A_REG 0xB0 /* Video n Coefficient Set C4A Register */
60 #define VNC4B_REG 0xB4 /* Video n Coefficient Set C4B Register */
61 #define VNC4C_REG 0xB8 /* Video n Coefficient Set C4C Register */
62 #define VNC5A_REG 0xC0 /* Video n Coefficient Set C5A Register */
63 #define VNC5B_REG 0xC4 /* Video n Coefficient Set C5B Register */
64 #define VNC5C_REG 0xC8 /* Video n Coefficient Set C5C Register */
65 #define VNC6A_REG 0xD0 /* Video n Coefficient Set C6A Register */
66 #define VNC6B_REG 0xD4 /* Video n Coefficient Set C6B Register */
67 #define VNC6C_REG 0xD8 /* Video n Coefficient Set C6C Register */
68 #define VNC7A_REG 0xE0 /* Video n Coefficient Set C7A Register */
69 #define VNC7B_REG 0xE4 /* Video n Coefficient Set C7B Register */
70 #define VNC7C_REG 0xE8 /* Video n Coefficient Set C7C Register */
71 #define VNC8A_REG 0xF0 /* Video n Coefficient Set C8A Register */
72 #define VNC8B_REG 0xF4 /* Video n Coefficient Set C8B Register */
73 #define VNC8C_REG 0xF8 /* Video n Coefficient Set C8C Register */
76 #define VNCSI_IFMD_REG 0x20 /* Video n CSI2 Interface Mode Register */
85 #define VNMC_INF_YUV8_BT656 (0 << 16)
94 #define VNMC_IM_ODD (0 << 3)
99 #define VNMC_ME (1 << 0)
106 #define VNMS_CA (1 << 0)
110 #define VNFC_S_FRAME (1 << 0)
120 #define VNDMR_A8BIT(n) (((n) & 0xff) << 24)
121 #define VNDMR_A8BIT_MASK (0xff << 24)
127 #define VNDMR_DTMD_ARGB (1 << 0)
128 #define VNDMR_DTMD_YCSEP_420 (3 << 0)
136 #define VNDMR2_VLV(n) ((n & 0xf) << 12)
141 #define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
172 { 0x0000, {
173 0x00000000, 0x00000000, 0x00000000,
174 0x00000000, 0x00000000, 0x00000000,
175 0x00000000, 0x00000000, 0x00000000,
176 0x00000000, 0x00000000, 0x00000000,
177 0x00000000, 0x00000000, 0x00000000,
178 0x00000000, 0x00000000, 0x00000000,
179 0x00000000, 0x00000000, 0x00000000,
180 0x00000000, 0x00000000, 0x00000000 },
182 { 0x1000, {
183 0x000fa400, 0x000fa400, 0x09625902,
184 0x000003f8, 0x00000403, 0x3de0d9f0,
185 0x001fffed, 0x00000804, 0x3cc1f9c3,
186 0x001003de, 0x00000c01, 0x3cb34d7f,
187 0x002003d2, 0x00000c00, 0x3d24a92d,
188 0x00200bca, 0x00000bff, 0x3df600d2,
189 0x002013cc, 0x000007ff, 0x3ed70c7e,
190 0x00100fde, 0x00000000, 0x3f87c036 },
192 { 0x1200, {
193 0x002ffff1, 0x002ffff1, 0x02a0a9c8,
194 0x002003e7, 0x001ffffa, 0x000185bc,
195 0x002007dc, 0x000003ff, 0x3e52859c,
196 0x00200bd4, 0x00000002, 0x3d53996b,
197 0x00100fd0, 0x00000403, 0x3d04ad2d,
198 0x00000bd5, 0x00000403, 0x3d35ace7,
199 0x3ff003e4, 0x00000801, 0x3dc674a1,
200 0x3fffe800, 0x00000800, 0x3e76f461 },
202 { 0x1400, {
203 0x00100be3, 0x00100be3, 0x04d1359a,
204 0x00000fdb, 0x002003ed, 0x0211fd93,
205 0x00000fd6, 0x002003f4, 0x0002d97b,
206 0x000007d6, 0x002ffffb, 0x3e93b956,
207 0x3ff003da, 0x001003ff, 0x3db49926,
208 0x3fffefe9, 0x00100001, 0x3d655cee,
209 0x3fffd400, 0x00000003, 0x3d65f4b6,
210 0x000fb421, 0x00000402, 0x3dc6547e },
212 { 0x1600, {
213 0x00000bdd, 0x00000bdd, 0x06519578,
214 0x3ff007da, 0x00000be3, 0x03c24973,
215 0x3ff003d9, 0x00000be9, 0x01b30d5f,
216 0x3ffff7df, 0x001003f1, 0x0003c542,
217 0x000fdfec, 0x001003f7, 0x3ec4711d,
218 0x000fc400, 0x002ffffd, 0x3df504f1,
219 0x001fa81a, 0x002ffc00, 0x3d957cc2,
220 0x002f8c3c, 0x00100000, 0x3db5c891 },
222 { 0x1800, {
223 0x3ff003dc, 0x3ff003dc, 0x0791e558,
224 0x000ff7dd, 0x3ff007de, 0x05328554,
225 0x000fe7e3, 0x3ff00be2, 0x03232546,
226 0x000fd7ee, 0x000007e9, 0x0143bd30,
227 0x001fb800, 0x000007ee, 0x00044511,
228 0x002fa015, 0x000007f4, 0x3ef4bcee,
229 0x002f8832, 0x001003f9, 0x3e4514c7,
230 0x001f7853, 0x001003fd, 0x3de54c9f },
232 { 0x1a00, {
233 0x000fefe0, 0x000fefe0, 0x08721d3c,
234 0x001fdbe7, 0x000ffbde, 0x0652a139,
235 0x001fcbf0, 0x000003df, 0x0463292e,
236 0x002fb3ff, 0x3ff007e3, 0x0293a91d,
237 0x002f9c12, 0x3ff00be7, 0x01241905,
238 0x001f8c29, 0x000007ed, 0x3fe470eb,
239 0x000f7c46, 0x000007f2, 0x3f04b8ca,
240 0x3fef7865, 0x000007f6, 0x3e74e4a8 },
242 { 0x1c00, {
243 0x001fd3e9, 0x001fd3e9, 0x08f23d26,
244 0x002fbff3, 0x001fe3e4, 0x0712ad23,
245 0x002fa800, 0x000ff3e0, 0x05631d1b,
246 0x001f9810, 0x000ffbe1, 0x03b3890d,
247 0x000f8c23, 0x000003e3, 0x0233e8fa,
248 0x3fef843b, 0x000003e7, 0x00f430e4,
249 0x3fbf8456, 0x3ff00bea, 0x00046cc8,
250 0x3f8f8c72, 0x3ff00bef, 0x3f3490ac },
252 { 0x1e00, {
253 0x001fbbf4, 0x001fbbf4, 0x09425112,
254 0x001fa800, 0x002fc7ed, 0x0792b110,
255 0x000f980e, 0x001fdbe6, 0x0613110a,
256 0x3fff8c20, 0x001fe7e3, 0x04a368fd,
257 0x3fcf8c33, 0x000ff7e2, 0x0343b8ed,
258 0x3f9f8c4a, 0x000fffe3, 0x0203f8da,
259 0x3f5f9c61, 0x000003e6, 0x00e428c5,
260 0x3f1fb07b, 0x000003eb, 0x3fe440af },
262 { 0x2000, {
263 0x000fa400, 0x000fa400, 0x09625902,
264 0x3fff980c, 0x001fb7f5, 0x0812b0ff,
265 0x3fdf901c, 0x001fc7ed, 0x06b2fcfa,
266 0x3faf902d, 0x001fd3e8, 0x055348f1,
267 0x3f7f983f, 0x001fe3e5, 0x04038ce3,
268 0x3f3fa454, 0x001fefe3, 0x02e3c8d1,
269 0x3f0fb86a, 0x001ff7e4, 0x01c3e8c0,
270 0x3ecfd880, 0x000fffe6, 0x00c404ac },
272 { 0x2200, {
273 0x3fdf9c0b, 0x3fdf9c0b, 0x09725cf4,
274 0x3fbf9818, 0x3fffa400, 0x0842a8f1,
275 0x3f8f9827, 0x000fb3f7, 0x0702f0ec,
276 0x3f5fa037, 0x000fc3ef, 0x05d330e4,
277 0x3f2fac49, 0x001fcfea, 0x04a364d9,
278 0x3effc05c, 0x001fdbe7, 0x038394ca,
279 0x3ecfdc6f, 0x001fe7e6, 0x0273b0bb,
280 0x3ea00083, 0x001fefe6, 0x0183c0a9 },
282 { 0x2400, {
283 0x3f9fa014, 0x3f9fa014, 0x098260e6,
284 0x3f7f9c23, 0x3fcf9c0a, 0x08629ce5,
285 0x3f4fa431, 0x3fefa400, 0x0742d8e1,
286 0x3f1fb440, 0x3fffb3f8, 0x062310d9,
287 0x3eefc850, 0x000fbbf2, 0x050340d0,
288 0x3ecfe062, 0x000fcbec, 0x041364c2,
289 0x3ea00073, 0x001fd3ea, 0x03037cb5,
290 0x3e902086, 0x001fdfe8, 0x022388a5 },
292 { 0x2600, {
293 0x3f5fa81e, 0x3f5fa81e, 0x096258da,
294 0x3f3fac2b, 0x3f8fa412, 0x088290d8,
295 0x3f0fbc38, 0x3fafa408, 0x0772c8d5,
296 0x3eefcc47, 0x3fcfa800, 0x0672f4ce,
297 0x3ecfe456, 0x3fefaffa, 0x05531cc6,
298 0x3eb00066, 0x3fffbbf3, 0x047334bb,
299 0x3ea01c77, 0x000fc7ee, 0x039348ae,
300 0x3ea04486, 0x000fd3eb, 0x02b350a1 },
302 { 0x2800, {
303 0x3f2fb426, 0x3f2fb426, 0x094250ce,
304 0x3f0fc032, 0x3f4fac1b, 0x086284cd,
305 0x3eefd040, 0x3f7fa811, 0x0782acc9,
306 0x3ecfe84c, 0x3f9fa807, 0x06a2d8c4,
307 0x3eb0005b, 0x3fbfac00, 0x05b2f4bc,
308 0x3eb0186a, 0x3fdfb3fa, 0x04c308b4,
309 0x3eb04077, 0x3fefbbf4, 0x03f31ca8,
310 0x3ec06884, 0x000fbff2, 0x03031c9e },
312 { 0x2a00, {
313 0x3f0fc42d, 0x3f0fc42d, 0x090240c4,
314 0x3eefd439, 0x3f2fb822, 0x08526cc2,
315 0x3edfe845, 0x3f4fb018, 0x078294bf,
316 0x3ec00051, 0x3f6fac0f, 0x06b2b4bb,
317 0x3ec0185f, 0x3f8fac07, 0x05e2ccb4,
318 0x3ec0386b, 0x3fafac00, 0x0502e8ac,
319 0x3ed05c77, 0x3fcfb3fb, 0x0432f0a3,
320 0x3ef08482, 0x3fdfbbf6, 0x0372f898 },
322 { 0x2c00, {
323 0x3eefdc31, 0x3eefdc31, 0x08e238b8,
324 0x3edfec3d, 0x3f0fc828, 0x082258b9,
325 0x3ed00049, 0x3f1fc01e, 0x077278b6,
326 0x3ed01455, 0x3f3fb815, 0x06c294b2,
327 0x3ed03460, 0x3f5fb40d, 0x0602acac,
328 0x3ef0506c, 0x3f7fb006, 0x0542c0a4,
329 0x3f107476, 0x3f9fb400, 0x0472c89d,
330 0x3f309c80, 0x3fbfb7fc, 0x03b2cc94 },
332 { 0x2e00, {
333 0x3eefec37, 0x3eefec37, 0x088220b0,
334 0x3ee00041, 0x3effdc2d, 0x07f244ae,
335 0x3ee0144c, 0x3f0fd023, 0x07625cad,
336 0x3ef02c57, 0x3f1fc81a, 0x06c274a9,
337 0x3f004861, 0x3f3fbc13, 0x060288a6,
338 0x3f20686b, 0x3f5fb80c, 0x05529c9e,
339 0x3f408c74, 0x3f6fb805, 0x04b2ac96,
340 0x3f80ac7e, 0x3f8fb800, 0x0402ac8e },
342 { 0x3000, {
343 0x3ef0003a, 0x3ef0003a, 0x084210a6,
344 0x3ef01045, 0x3effec32, 0x07b228a7,
345 0x3f00284e, 0x3f0fdc29, 0x073244a4,
346 0x3f104058, 0x3f0fd420, 0x06a258a2,
347 0x3f305c62, 0x3f2fc818, 0x0612689d,
348 0x3f508069, 0x3f3fc011, 0x05728496,
349 0x3f80a072, 0x3f4fc00a, 0x04d28c90,
350 0x3fc0c07b, 0x3f6fbc04, 0x04429088 },
352 { 0x3200, {
353 0x3f00103e, 0x3f00103e, 0x07f1fc9e,
354 0x3f102447, 0x3f000035, 0x0782149d,
355 0x3f203c4f, 0x3f0ff02c, 0x07122c9c,
356 0x3f405458, 0x3f0fe424, 0x06924099,
357 0x3f607061, 0x3f1fd41d, 0x06024c97,
358 0x3f909068, 0x3f2fcc16, 0x05726490,
359 0x3fc0b070, 0x3f3fc80f, 0x04f26c8a,
360 0x0000d077, 0x3f4fc409, 0x04627484 },
362 { 0x3400, {
363 0x3f202040, 0x3f202040, 0x07a1e898,
364 0x3f303449, 0x3f100c38, 0x0741fc98,
365 0x3f504c50, 0x3f10002f, 0x06e21495,
366 0x3f706459, 0x3f1ff028, 0x06722492,
367 0x3fa08060, 0x3f1fe421, 0x05f2348f,
368 0x3fd09c67, 0x3f1fdc19, 0x05824c89,
369 0x0000bc6e, 0x3f2fd014, 0x04f25086,
370 0x0040dc74, 0x3f3fcc0d, 0x04825c7f },
372 { 0x3600, {
373 0x3f403042, 0x3f403042, 0x0761d890,
374 0x3f504848, 0x3f301c3b, 0x0701f090,
375 0x3f805c50, 0x3f200c33, 0x06a2008f,
376 0x3fa07458, 0x3f10002b, 0x06520c8d,
377 0x3fd0905e, 0x3f1ff424, 0x05e22089,
378 0x0000ac65, 0x3f1fe81d, 0x05823483,
379 0x0030cc6a, 0x3f2fdc18, 0x04f23c81,
380 0x0080e871, 0x3f2fd412, 0x0482407c },
382 { 0x3800, {
383 0x3f604043, 0x3f604043, 0x0721c88a,
384 0x3f80544a, 0x3f502c3c, 0x06d1d88a,
385 0x3fb06851, 0x3f301c35, 0x0681e889,
386 0x3fd08456, 0x3f30082f, 0x0611fc88,
387 0x00009c5d, 0x3f200027, 0x05d20884,
388 0x0030b863, 0x3f2ff421, 0x05621880,
389 0x0070d468, 0x3f2fe81b, 0x0502247c,
390 0x00c0ec6f, 0x3f2fe015, 0x04a22877 },
392 { 0x3a00, {
393 0x3f904c44, 0x3f904c44, 0x06e1b884,
394 0x3fb0604a, 0x3f70383e, 0x0691c885,
395 0x3fe07451, 0x3f502c36, 0x0661d483,
396 0x00009055, 0x3f401831, 0x0601ec81,
397 0x0030a85b, 0x3f300c2a, 0x05b1f480,
398 0x0070c061, 0x3f300024, 0x0562047a,
399 0x00b0d867, 0x3f3ff41e, 0x05020c77,
400 0x00f0f46b, 0x3f2fec19, 0x04a21474 },
402 { 0x3c00, {
403 0x3fb05c43, 0x3fb05c43, 0x06c1b07e,
404 0x3fe06c4b, 0x3f902c3f, 0x0681c081,
405 0x0000844f, 0x3f703838, 0x0631cc7d,
406 0x00309855, 0x3f602433, 0x05d1d47e,
407 0x0060b459, 0x3f50142e, 0x0581e47b,
408 0x00a0c85f, 0x3f400828, 0x0531f078,
409 0x00e0e064, 0x3f300021, 0x0501fc73,
410 0x00b0fc6a, 0x3f3ff41d, 0x04a20873 },
412 { 0x3e00, {
413 0x3fe06444, 0x3fe06444, 0x0681a07a,
414 0x00007849, 0x3fc0503f, 0x0641b07a,
415 0x0020904d, 0x3fa0403a, 0x05f1c07a,
416 0x0060a453, 0x3f803034, 0x05c1c878,
417 0x0090b858, 0x3f70202f, 0x0571d477,
418 0x00d0d05d, 0x3f501829, 0x0531e073,
419 0x0110e462, 0x3f500825, 0x04e1e471,
420 0x01510065, 0x3f40001f, 0x04a1f06d },
422 { 0x4000, {
423 0x00007044, 0x00007044, 0x06519476,
424 0x00208448, 0x3fe05c3f, 0x0621a476,
425 0x0050984d, 0x3fc04c3a, 0x05e1b075,
426 0x0080ac52, 0x3fa03c35, 0x05a1b875,
427 0x00c0c056, 0x3f803030, 0x0561c473,
428 0x0100d45b, 0x3f70202b, 0x0521d46f,
429 0x0140e860, 0x3f601427, 0x04d1d46e,
430 0x01810064, 0x3f500822, 0x0491dc6b },
432 { 0x5000, {
433 0x0110a442, 0x0110a442, 0x0551545e,
434 0x0140b045, 0x00e0983f, 0x0531585f,
435 0x0160c047, 0x00c08c3c, 0x0511645e,
436 0x0190cc4a, 0x00908039, 0x04f1685f,
437 0x01c0dc4c, 0x00707436, 0x04d1705e,
438 0x0200e850, 0x00506833, 0x04b1785b,
439 0x0230f453, 0x00305c30, 0x0491805a,
440 0x02710056, 0x0010542d, 0x04718059 },
442 { 0x6000, {
443 0x01c0bc40, 0x01c0bc40, 0x04c13052,
444 0x01e0c841, 0x01a0b43d, 0x04c13851,
445 0x0210cc44, 0x0180a83c, 0x04a13453,
446 0x0230d845, 0x0160a03a, 0x04913c52,
447 0x0260e047, 0x01409838, 0x04714052,
448 0x0280ec49, 0x01208c37, 0x04514c50,
449 0x02b0f44b, 0x01008435, 0x04414c50,
450 0x02d1004c, 0x00e07c33, 0x0431544f },
452 { 0x7000, {
453 0x0230c83e, 0x0230c83e, 0x04711c4c,
454 0x0250d03f, 0x0210c43c, 0x0471204b,
455 0x0270d840, 0x0200b83c, 0x0451244b,
456 0x0290dc42, 0x01e0b43a, 0x0441244c,
457 0x02b0e443, 0x01c0b038, 0x0441284b,
458 0x02d0ec44, 0x01b0a438, 0x0421304a,
459 0x02f0f445, 0x0190a036, 0x04213449,
460 0x0310f847, 0x01709c34, 0x04213848 },
462 { 0x8000, {
463 0x0280d03d, 0x0280d03d, 0x04310c48,
464 0x02a0d43e, 0x0270c83c, 0x04311047,
465 0x02b0dc3e, 0x0250c83a, 0x04311447,
466 0x02d0e040, 0x0240c03a, 0x04211446,
467 0x02e0e840, 0x0220bc39, 0x04111847,
468 0x0300e842, 0x0210b438, 0x04012445,
469 0x0310f043, 0x0200b037, 0x04012045,
470 0x0330f444, 0x01e0ac36, 0x03f12445 },
472 { 0xefff, {
473 0x0340dc3a, 0x0340dc3a, 0x03b0ec40,
474 0x0340e03a, 0x0330e039, 0x03c0f03e,
475 0x0350e03b, 0x0330dc39, 0x03c0ec3e,
476 0x0350e43a, 0x0320dc38, 0x03c0f43e,
477 0x0360e43b, 0x0320d839, 0x03b0f03e,
478 0x0360e83b, 0x0310d838, 0x03c0fc3b,
479 0x0370e83b, 0x0310d439, 0x03a0f83d,
480 0x0370e83c, 0x0300d438, 0x03b0fc3c },
491 for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) { in rvin_set_coeff()
505 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
548 ys = 0; in rvin_crop_scale_comp_gen2()
553 xs = 0; in rvin_crop_scale_comp_gen2()
558 if (xs > 0 && xs < 2048) in rvin_crop_scale_comp_gen2()
570 rvin_write(vin, 0, VNSPPOC_REG); in rvin_crop_scale_comp_gen2()
571 rvin_write(vin, 0, VNSLPOC_REG); in rvin_crop_scale_comp_gen2()
583 0, 0); in rvin_crop_scale_comp_gen2()
773 0x80), VNUVAOF_REG); in rvin_setup()
783 dmr = 0; in rvin_setup()
790 dmr = 0; in rvin_setup()
797 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
806 dmr = 0; in rvin_setup()
813 dmr = 0; in rvin_setup()
817 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
853 return 0; in rvin_setup()
858 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
931 prev = (slot == 0 ? HW_BUFFER_NUM : slot) - 1; in rvin_fill_hw_slot()
965 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); in rvin_fill_hw_slot()
979 for (slot = 0; slot < HW_BUFFER_NUM; slot++) { in rvin_capture_start()
984 for (slot = 0; slot < HW_BUFFER_NUM; slot++) in rvin_capture_start()
1000 return 0; in rvin_capture_start()
1006 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
1024 unsigned int handled = 0; in rvin_irq()
1052 * to capture first from slot 0. in rvin_irq()
1055 if (slot != 0) { in rvin_irq()
1123 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1126 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1128 return 0; in rvin_queue_setup()
1136 if (vb2_plane_size(vb, 0) < size) { in rvin_buffer_prepare()
1138 vb2_plane_size(vb, 0), size); in rvin_buffer_prepare()
1142 vb2_set_plane_payload(vb, 0, size); in rvin_buffer_prepare()
1144 return 0; in rvin_buffer_prepare()
1242 return 0; in rvin_mc_validate_format()
1256 return ret == -ENOIOCTLCMD ? 0 : ret; in rvin_set_stream()
1267 return v4l2_subdev_call(sd, video, s_stream, 0); in rvin_set_stream()
1280 ret = 0; in rvin_set_stream()
1298 vin->sequence = 0; in rvin_start_streaming()
1302 rvin_set_stream(vin, 0); in rvin_start_streaming()
1324 return 0; in rvin_start_streaming_vq()
1350 retries = 0; in rvin_stop_streaming()
1353 for (i = 0; i < HW_BUFFER_NUM; i++) in rvin_stop_streaming()
1366 retries = 0; in rvin_stop_streaming()
1397 for (i = 0; i < HW_BUFFER_NUM; i++) { in rvin_stop_streaming()
1404 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1457 for (i = 0; i < HW_BUFFER_NUM; i++) in rvin_dma_register()
1473 if (ret < 0) { in rvin_dma_register()
1486 return 0; in rvin_dma_register()
1505 u32 ifmd = 0; in rvin_set_channel_routing()
1510 if (ret < 0) in rvin_set_channel_routing()
1518 * Set data expansion mode to "pad with 0s" by inspecting the routes in rvin_set_channel_routing()
1538 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1547 return 0; in rvin_set_channel_routing()