Lines Matching +full:0 +full:x00ffffff
13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
36 #define BM_PXP_CTRL_ENABLE_LUT 0x02000000
39 #define BM_PXP_CTRL_ENABLE_CSC2 0x01000000
42 #define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
45 #define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0
46 #define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
47 #define BM_PXP_CTRL_RSVD1 0x00400000
50 #define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000
53 #define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000
56 #define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000
59 #define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000
62 #define BM_PXP_CTRL_ENABLE_DITHER 0x00020000
65 #define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000
68 #define BM_PXP_CTRL_VFLIP1 0x00008000
71 #define BM_PXP_CTRL_HFLIP1 0x00004000
75 #define BM_PXP_CTRL_ROTATE1 0x00003000
78 #define BV_PXP_CTRL_ROTATE1__ROT_0 0x0
79 #define BV_PXP_CTRL_ROTATE1__ROT_90 0x1
80 #define BV_PXP_CTRL_ROTATE1__ROT_180 0x2
81 #define BV_PXP_CTRL_ROTATE1__ROT_270 0x3
82 #define BM_PXP_CTRL_VFLIP0 0x00000800
85 #define BM_PXP_CTRL_HFLIP0 0x00000400
89 #define BM_PXP_CTRL_ROTATE0 0x00000300
92 #define BV_PXP_CTRL_ROTATE0__ROT_0 0x0
93 #define BV_PXP_CTRL_ROTATE0__ROT_90 0x1
94 #define BV_PXP_CTRL_ROTATE0__ROT_180 0x2
95 #define BV_PXP_CTRL_ROTATE0__ROT_270 0x3
97 #define BM_PXP_CTRL_RSVD0 0x000000C0
100 #define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020
103 #define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010
106 #define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008
109 #define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
112 #define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
115 #define BM_PXP_CTRL_ENABLE 0x00000001
117 (((v) << 0) & BM_PXP_CTRL_ENABLE)
119 #define HW_PXP_STAT (0x00000010)
120 #define HW_PXP_STAT_SET (0x00000014)
121 #define HW_PXP_STAT_CLR (0x00000018)
122 #define HW_PXP_STAT_TOG (0x0000001c)
125 #define BM_PXP_STAT_BLOCKX 0xFF000000
129 #define BM_PXP_STAT_BLOCKY 0x00FF0000
133 #define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000
136 #define BM_PXP_STAT_RSVD2 0x00000800
139 #define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400
142 #define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200
145 #define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100
149 #define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0
152 #define BM_PXP_STAT_NEXT_IRQ 0x00000008
155 #define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004
158 #define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002
161 #define BM_PXP_STAT_IRQ0 0x00000001
163 (((v) << 0) & BM_PXP_STAT_IRQ0)
165 #define HW_PXP_OUT_CTRL (0x00000020)
166 #define HW_PXP_OUT_CTRL_SET (0x00000024)
167 #define HW_PXP_OUT_CTRL_CLR (0x00000028)
168 #define HW_PXP_OUT_CTRL_TOG (0x0000002c)
171 #define BM_PXP_OUT_CTRL_ALPHA 0xFF000000
174 #define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000
178 #define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00
182 #define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300
185 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
186 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1
187 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2
188 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3
190 #define BM_PXP_OUT_CTRL_RSVD0 0x000000E0
193 #define BP_PXP_OUT_CTRL_FORMAT 0
194 #define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
196 (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
197 #define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0
198 #define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4
199 #define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5
200 #define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8
201 #define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9
202 #define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC
203 #define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD
204 #define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE
205 #define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10
206 #define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
207 #define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
208 #define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14
209 #define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15
210 #define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18
211 #define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19
212 #define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A
213 #define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B
215 #define HW_PXP_OUT_BUF (0x00000030)
217 #define BP_PXP_OUT_BUF_ADDR 0
218 #define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF
221 #define HW_PXP_OUT_BUF2 (0x00000040)
223 #define BP_PXP_OUT_BUF2_ADDR 0
224 #define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF
227 #define HW_PXP_OUT_PITCH (0x00000050)
230 #define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000
233 #define BP_PXP_OUT_PITCH_PITCH 0
234 #define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF
236 (((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
238 #define HW_PXP_OUT_LRC (0x00000060)
241 #define BM_PXP_OUT_LRC_RSVD1 0xC0000000
245 #define BM_PXP_OUT_LRC_X 0x3FFF0000
249 #define BM_PXP_OUT_LRC_RSVD0 0x0000C000
252 #define BP_PXP_OUT_LRC_Y 0
253 #define BM_PXP_OUT_LRC_Y 0x00003FFF
255 (((v) << 0) & BM_PXP_OUT_LRC_Y)
257 #define HW_PXP_OUT_PS_ULC (0x00000070)
260 #define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000
264 #define BM_PXP_OUT_PS_ULC_X 0x3FFF0000
268 #define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000
271 #define BP_PXP_OUT_PS_ULC_Y 0
272 #define BM_PXP_OUT_PS_ULC_Y 0x00003FFF
274 (((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
276 #define HW_PXP_OUT_PS_LRC (0x00000080)
279 #define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000
283 #define BM_PXP_OUT_PS_LRC_X 0x3FFF0000
287 #define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000
290 #define BP_PXP_OUT_PS_LRC_Y 0
291 #define BM_PXP_OUT_PS_LRC_Y 0x00003FFF
293 (((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
295 #define HW_PXP_OUT_AS_ULC (0x00000090)
298 #define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000
302 #define BM_PXP_OUT_AS_ULC_X 0x3FFF0000
306 #define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000
309 #define BP_PXP_OUT_AS_ULC_Y 0
310 #define BM_PXP_OUT_AS_ULC_Y 0x00003FFF
312 (((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
314 #define HW_PXP_OUT_AS_LRC (0x000000a0)
317 #define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000
321 #define BM_PXP_OUT_AS_LRC_X 0x3FFF0000
325 #define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000
328 #define BP_PXP_OUT_AS_LRC_Y 0
329 #define BM_PXP_OUT_AS_LRC_Y 0x00003FFF
331 (((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
333 #define HW_PXP_PS_CTRL (0x000000b0)
334 #define HW_PXP_PS_CTRL_SET (0x000000b4)
335 #define HW_PXP_PS_CTRL_CLR (0x000000b8)
336 #define HW_PXP_PS_CTRL_TOG (0x000000bc)
339 #define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000
343 #define BM_PXP_PS_CTRL_DECX 0x00000C00
346 #define BV_PXP_PS_CTRL_DECX__DISABLE 0x0
347 #define BV_PXP_PS_CTRL_DECX__DECX2 0x1
348 #define BV_PXP_PS_CTRL_DECX__DECX4 0x2
349 #define BV_PXP_PS_CTRL_DECX__DECX8 0x3
351 #define BM_PXP_PS_CTRL_DECY 0x00000300
354 #define BV_PXP_PS_CTRL_DECY__DISABLE 0x0
355 #define BV_PXP_PS_CTRL_DECY__DECY2 0x1
356 #define BV_PXP_PS_CTRL_DECY__DECY4 0x2
357 #define BV_PXP_PS_CTRL_DECY__DECY8 0x3
358 #define BM_PXP_PS_CTRL_RSVD0 0x00000080
361 #define BM_PXP_PS_CTRL_WB_SWAP 0x00000040
364 #define BP_PXP_PS_CTRL_FORMAT 0
365 #define BM_PXP_PS_CTRL_FORMAT 0x0000003F
367 (((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
368 #define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4
369 #define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC
370 #define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD
371 #define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE
372 #define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10
373 #define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
374 #define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
375 #define BV_PXP_PS_CTRL_FORMAT__Y8 0x14
376 #define BV_PXP_PS_CTRL_FORMAT__Y4 0x15
377 #define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18
378 #define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19
379 #define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A
380 #define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B
381 #define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E
382 #define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F
384 #define HW_PXP_PS_BUF (0x000000c0)
386 #define BP_PXP_PS_BUF_ADDR 0
387 #define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF
390 #define HW_PXP_PS_UBUF (0x000000d0)
392 #define BP_PXP_PS_UBUF_ADDR 0
393 #define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF
396 #define HW_PXP_PS_VBUF (0x000000e0)
398 #define BP_PXP_PS_VBUF_ADDR 0
399 #define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF
402 #define HW_PXP_PS_PITCH (0x000000f0)
405 #define BM_PXP_PS_PITCH_RSVD 0xFFFF0000
408 #define BP_PXP_PS_PITCH_PITCH 0
409 #define BM_PXP_PS_PITCH_PITCH 0x0000FFFF
411 (((v) << 0) & BM_PXP_PS_PITCH_PITCH)
413 #define HW_PXP_PS_BACKGROUND_0 (0x00000100)
416 #define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000
419 #define BP_PXP_PS_BACKGROUND_0_COLOR 0
420 #define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF
422 (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR)
424 #define HW_PXP_PS_SCALE (0x00000110)
426 #define BM_PXP_PS_SCALE_RSVD2 0x80000000
430 #define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
433 #define BM_PXP_PS_SCALE_RSVD1 0x00008000
436 #define BP_PXP_PS_SCALE_XSCALE 0
437 #define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
439 (((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
441 #define HW_PXP_PS_OFFSET (0x00000120)
444 #define BM_PXP_PS_OFFSET_RSVD2 0xF0000000
448 #define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000
452 #define BM_PXP_PS_OFFSET_RSVD1 0x0000F000
455 #define BP_PXP_PS_OFFSET_XOFFSET 0
456 #define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF
458 (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
460 #define HW_PXP_PS_CLRKEYLOW_0 (0x00000130)
463 #define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000
466 #define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0
467 #define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF
469 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL)
471 #define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140)
474 #define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000
477 #define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0
478 #define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF
480 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL)
482 #define HW_PXP_AS_CTRL (0x00000150)
485 #define BM_PXP_AS_CTRL_RSVD1 0xFFC00000
488 #define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000
491 #define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000
495 #define BM_PXP_AS_CTRL_ROP 0x000F0000
498 #define BV_PXP_AS_CTRL_ROP__MASKAS 0x0
499 #define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1
500 #define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2
501 #define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3
502 #define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4
503 #define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5
504 #define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6
505 #define BV_PXP_AS_CTRL_ROP__NOT 0x7
506 #define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8
507 #define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9
508 #define BV_PXP_AS_CTRL_ROP__XORAS 0xA
509 #define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB
511 #define BM_PXP_AS_CTRL_ALPHA 0x0000FF00
515 #define BM_PXP_AS_CTRL_FORMAT 0x000000F0
518 #define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0
519 #define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1
520 #define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4
521 #define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8
522 #define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9
523 #define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC
524 #define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD
525 #define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE
526 #define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008
530 #define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006
533 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0
534 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1
535 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2
536 #define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3
537 #define BM_PXP_AS_CTRL_RSVD0 0x00000001
539 (((v) << 0) & BM_PXP_AS_CTRL_RSVD0)
541 #define HW_PXP_AS_BUF (0x00000160)
543 #define BP_PXP_AS_BUF_ADDR 0
544 #define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF
547 #define HW_PXP_AS_PITCH (0x00000170)
550 #define BM_PXP_AS_PITCH_RSVD 0xFFFF0000
553 #define BP_PXP_AS_PITCH_PITCH 0
554 #define BM_PXP_AS_PITCH_PITCH 0x0000FFFF
556 (((v) << 0) & BM_PXP_AS_PITCH_PITCH)
558 #define HW_PXP_AS_CLRKEYLOW_0 (0x00000180)
561 #define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000
564 #define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0
565 #define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF
567 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL)
569 #define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190)
572 #define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000
575 #define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0
576 #define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF
578 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL)
580 #define HW_PXP_CSC1_COEF0 (0x000001a0)
582 #define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000
585 #define BM_PXP_CSC1_COEF0_BYPASS 0x40000000
588 #define BM_PXP_CSC1_COEF0_RSVD1 0x20000000
592 #define BM_PXP_CSC1_COEF0_C0 0x1FFC0000
596 #define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00
599 #define BP_PXP_CSC1_COEF0_Y_OFFSET 0
600 #define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF
602 (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET)
604 #define HW_PXP_CSC1_COEF1 (0x000001b0)
607 #define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000
611 #define BM_PXP_CSC1_COEF1_C1 0x07FF0000
615 #define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800
618 #define BP_PXP_CSC1_COEF1_C4 0
619 #define BM_PXP_CSC1_COEF1_C4 0x000007FF
621 (((v) << 0) & BM_PXP_CSC1_COEF1_C4)
623 #define HW_PXP_CSC1_COEF2 (0x000001c0)
626 #define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000
630 #define BM_PXP_CSC1_COEF2_C2 0x07FF0000
634 #define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800
637 #define BP_PXP_CSC1_COEF2_C3 0
638 #define BM_PXP_CSC1_COEF2_C3 0x000007FF
640 (((v) << 0) & BM_PXP_CSC1_COEF2_C3)
642 #define HW_PXP_CSC2_CTRL (0x000001d0)
645 #define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8
649 #define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006
652 #define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0
653 #define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1
654 #define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2
655 #define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3
656 #define BM_PXP_CSC2_CTRL_BYPASS 0x00000001
658 (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS)
660 #define HW_PXP_CSC2_COEF0 (0x000001e0)
663 #define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000
667 #define BM_PXP_CSC2_COEF0_A2 0x07FF0000
671 #define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800
674 #define BP_PXP_CSC2_COEF0_A1 0
675 #define BM_PXP_CSC2_COEF0_A1 0x000007FF
677 (((v) << 0) & BM_PXP_CSC2_COEF0_A1)
679 #define HW_PXP_CSC2_COEF1 (0x000001f0)
682 #define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000
686 #define BM_PXP_CSC2_COEF1_B1 0x07FF0000
690 #define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800
693 #define BP_PXP_CSC2_COEF1_A3 0
694 #define BM_PXP_CSC2_COEF1_A3 0x000007FF
696 (((v) << 0) & BM_PXP_CSC2_COEF1_A3)
698 #define HW_PXP_CSC2_COEF2 (0x00000200)
701 #define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000
705 #define BM_PXP_CSC2_COEF2_B3 0x07FF0000
709 #define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800
712 #define BP_PXP_CSC2_COEF2_B2 0
713 #define BM_PXP_CSC2_COEF2_B2 0x000007FF
715 (((v) << 0) & BM_PXP_CSC2_COEF2_B2)
717 #define HW_PXP_CSC2_COEF3 (0x00000210)
720 #define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000
724 #define BM_PXP_CSC2_COEF3_C2 0x07FF0000
728 #define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800
731 #define BP_PXP_CSC2_COEF3_C1 0
732 #define BM_PXP_CSC2_COEF3_C1 0x000007FF
734 (((v) << 0) & BM_PXP_CSC2_COEF3_C1)
736 #define HW_PXP_CSC2_COEF4 (0x00000220)
739 #define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000
743 #define BM_PXP_CSC2_COEF4_D1 0x01FF0000
747 #define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800
750 #define BP_PXP_CSC2_COEF4_C3 0
751 #define BM_PXP_CSC2_COEF4_C3 0x000007FF
753 (((v) << 0) & BM_PXP_CSC2_COEF4_C3)
755 #define HW_PXP_CSC2_COEF5 (0x00000230)
758 #define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000
762 #define BM_PXP_CSC2_COEF5_D3 0x01FF0000
766 #define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00
769 #define BP_PXP_CSC2_COEF5_D2 0
770 #define BM_PXP_CSC2_COEF5_D2 0x000001FF
772 (((v) << 0) & BM_PXP_CSC2_COEF5_D2)
774 #define HW_PXP_LUT_CTRL (0x00000240)
776 #define BM_PXP_LUT_CTRL_BYPASS 0x80000000
780 #define BM_PXP_LUT_CTRL_RSVD3 0x7C000000
784 #define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000
787 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0
788 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1
789 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2
790 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3
792 #define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000
796 #define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000
799 #define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0
800 #define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1
801 #define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2
802 #define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3
804 #define BM_PXP_LUT_CTRL_RSVD1 0x0000F800
807 #define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400
810 #define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200
813 #define BM_PXP_LUT_CTRL_INVALID 0x00000100
817 #define BM_PXP_LUT_CTRL_RSVD0 0x000000FE
820 #define BM_PXP_LUT_CTRL_DMA_START 0x00000001
822 (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START)
824 #define HW_PXP_LUT_ADDR (0x00000250)
826 #define BM_PXP_LUT_ADDR_RSVD2 0x80000000
830 #define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000
834 #define BM_PXP_LUT_ADDR_RSVD1 0x0000C000
837 #define BP_PXP_LUT_ADDR_ADDR 0
838 #define BM_PXP_LUT_ADDR_ADDR 0x00003FFF
840 (((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
842 #define HW_PXP_LUT_DATA (0x00000260)
844 #define BP_PXP_LUT_DATA_DATA 0
845 #define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF
848 #define HW_PXP_LUT_EXTMEM (0x00000270)
850 #define BP_PXP_LUT_EXTMEM_ADDR 0
851 #define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF
854 #define HW_PXP_CFA (0x00000280)
856 #define BP_PXP_CFA_DATA 0
857 #define BM_PXP_CFA_DATA 0xFFFFFFFF
860 #define HW_PXP_ALPHA_A_CTRL (0x00000290)
863 #define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000
867 #define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000
871 #define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000
874 #define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000
877 #define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0
878 #define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1
879 #define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000
882 #define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0
883 #define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1
885 #define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00
888 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0
889 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0
890 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0
891 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0
893 #define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300
896 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0
897 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1
898 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2
899 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3
900 #define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080
903 #define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040
906 #define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0
907 #define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1
908 #define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020
911 #define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0
912 #define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1
914 #define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018
917 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0
918 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1
919 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2
920 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3
922 #define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006
925 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0
926 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1
927 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2
928 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3
929 #define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001
931 (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE)
932 #define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0
933 #define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1
935 #define HW_PXP_ALPHA_B_CTRL (0x000002a0)
938 #define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000
942 #define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000
946 #define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000
949 #define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000
952 #define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0
953 #define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1
954 #define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000
957 #define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0
958 #define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1
960 #define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00
963 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0
964 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1
965 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2
966 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3
968 #define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300
971 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0
972 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1
973 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2
974 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3
975 #define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080
978 #define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040
981 #define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0
982 #define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1
983 #define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020
986 #define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0
987 #define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1
989 #define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018
992 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0
993 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1
994 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2
995 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3
997 #define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006
1000 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0
1001 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1
1002 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2
1003 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3
1004 #define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001
1006 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE)
1007 #define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0
1008 #define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1
1010 #define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0)
1013 #define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00
1017 #define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0
1020 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0
1021 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1
1022 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2
1023 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3
1024 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4
1025 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5
1026 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6
1027 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7
1028 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8
1029 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9
1030 #define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA
1031 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB
1033 #define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C
1036 #define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002
1039 #define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001
1041 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE)
1043 #define HW_PXP_PS_BACKGROUND_1 (0x000002c0)
1046 #define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000
1049 #define BP_PXP_PS_BACKGROUND_1_COLOR 0
1050 #define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF
1052 (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR)
1054 #define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0)
1057 #define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000
1060 #define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0
1061 #define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF
1063 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL)
1065 #define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0)
1068 #define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000
1071 #define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0
1072 #define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF
1074 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL)
1076 #define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0)
1079 #define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000
1082 #define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0
1083 #define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF
1085 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL)
1087 #define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300)
1090 #define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000
1093 #define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0
1094 #define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF
1096 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL)
1098 #define HW_PXP_CTRL2 (0x00000310)
1099 #define HW_PXP_CTRL2_SET (0x00000314)
1100 #define HW_PXP_CTRL2_CLR (0x00000318)
1101 #define HW_PXP_CTRL2_TOG (0x0000031c)
1104 #define BM_PXP_CTRL2_RSVD3 0xF0000000
1107 #define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000
1110 #define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000
1113 #define BM_PXP_CTRL2_ENABLE_LUT 0x02000000
1116 #define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000
1119 #define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000
1122 #define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0
1123 #define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1
1124 #define BM_PXP_CTRL2_RSVD2 0x00400000
1127 #define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000
1130 #define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000
1133 #define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000
1136 #define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000
1139 #define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000
1142 #define BM_PXP_CTRL2_RSVD1 0x00010000
1145 #define BM_PXP_CTRL2_VFLIP1 0x00008000
1148 #define BM_PXP_CTRL2_HFLIP1 0x00004000
1152 #define BM_PXP_CTRL2_ROTATE1 0x00003000
1155 #define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0
1156 #define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1
1157 #define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2
1158 #define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3
1159 #define BM_PXP_CTRL2_VFLIP0 0x00000800
1162 #define BM_PXP_CTRL2_HFLIP0 0x00000400
1166 #define BM_PXP_CTRL2_ROTATE0 0x00000300
1169 #define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0
1170 #define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1
1171 #define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2
1172 #define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3
1174 #define BM_PXP_CTRL2_RSVD0 0x000000FE
1177 #define BM_PXP_CTRL2_ENABLE 0x00000001
1179 (((v) << 0) & BM_PXP_CTRL2_ENABLE)
1181 #define HW_PXP_POWER_REG0 (0x00000320)
1184 #define BM_PXP_POWER_REG0_CTRL 0xFFFFF000
1188 #define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00
1191 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0
1192 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1
1193 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2
1194 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4
1196 #define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0
1199 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0
1200 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1
1201 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2
1202 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4
1204 #define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038
1207 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0
1208 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1
1209 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2
1210 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4
1211 #define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0
1212 #define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007
1214 (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0)
1215 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0
1216 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1
1217 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2
1218 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4
1220 #define HW_PXP_POWER_REG1 (0x00000330)
1223 #define BM_PXP_POWER_REG1_RSVD0 0xFF000000
1227 #define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000
1230 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0
1231 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1
1232 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2
1233 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4
1235 #define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000
1238 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0
1239 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1
1240 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2
1241 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4
1243 #define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000
1246 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0
1247 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1
1248 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2
1249 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4
1251 #define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000
1254 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0
1255 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1
1256 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2
1257 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4
1259 #define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00
1262 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0
1263 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1
1264 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2
1265 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4
1267 #define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0
1270 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0
1271 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1
1272 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2
1273 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4
1275 #define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038
1278 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0
1279 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1
1280 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2
1281 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4
1282 #define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0
1283 #define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007
1285 (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE)
1286 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0
1287 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1
1288 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2
1289 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4
1291 #define HW_PXP_DATA_PATH_CTRL0 (0x00000340)
1292 #define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344)
1293 #define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348)
1294 #define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c)
1297 #define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000
1300 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0
1301 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1
1302 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2
1303 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3
1305 #define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000
1308 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0
1309 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1
1310 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2
1311 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3
1313 #define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000
1316 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0
1317 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1
1318 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2
1319 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3
1321 #define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000
1324 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0
1325 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1
1326 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2
1327 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3
1329 #define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000
1332 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0
1333 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1
1334 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2
1335 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3
1337 #define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000
1340 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0
1341 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1
1342 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2
1343 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3
1345 #define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000
1348 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0
1349 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1
1350 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2
1351 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3
1353 #define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000
1356 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0
1357 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1
1358 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2
1359 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3
1361 #define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000
1364 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0
1365 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1
1366 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2
1367 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3
1369 #define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000
1372 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0
1373 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1
1374 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2
1375 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3
1377 #define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00
1380 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0
1381 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1
1382 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2
1383 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3
1385 #define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300
1388 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0
1389 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1
1390 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2
1391 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3
1393 #define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0
1396 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0
1397 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1
1398 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2
1399 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3
1401 #define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030
1404 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0
1405 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1
1406 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2
1407 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3
1409 #define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C
1412 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0
1413 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1
1414 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2
1415 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3
1416 #define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0
1417 #define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003
1419 (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL)
1420 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0
1421 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1
1422 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2
1423 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3
1425 #define HW_PXP_DATA_PATH_CTRL1 (0x00000350)
1426 #define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354)
1427 #define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358)
1428 #define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c)
1431 #define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0
1435 #define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C
1438 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0
1439 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1
1440 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2
1441 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3
1442 #define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0
1443 #define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003
1445 (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL)
1446 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0
1447 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1
1448 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2
1449 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3
1451 #define HW_PXP_INIT_MEM_CTRL (0x00000360)
1452 #define HW_PXP_INIT_MEM_CTRL_SET (0x00000364)
1453 #define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368)
1454 #define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c)
1456 #define BM_PXP_INIT_MEM_CTRL_START 0x80000000
1460 #define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000
1463 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0
1464 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1
1465 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2
1466 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3
1467 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4
1468 #define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5
1469 #define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6
1470 #define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7
1471 #define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8
1472 #define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15
1474 #define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000
1477 #define BP_PXP_INIT_MEM_CTRL_ADDR 0
1478 #define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF
1480 (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR)
1482 #define HW_PXP_INIT_MEM_DATA (0x00000370)
1484 #define BP_PXP_INIT_MEM_DATA_DATA 0
1485 #define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF
1488 #define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380)
1490 #define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0
1491 #define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF
1494 #define HW_PXP_IRQ_MASK (0x00000390)
1495 #define HW_PXP_IRQ_MASK_SET (0x00000394)
1496 #define HW_PXP_IRQ_MASK_CLR (0x00000398)
1497 #define HW_PXP_IRQ_MASK_TOG (0x0000039c)
1499 #define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000
1503 #define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000
1506 #define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000
1509 #define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000
1512 #define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000
1515 #define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000
1518 #define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800
1521 #define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400
1524 #define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200
1527 #define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100
1530 #define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080
1533 #define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040
1536 #define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020
1539 #define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010
1542 #define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008
1545 #define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004
1548 #define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002
1551 #define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001
1553 (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN)
1555 #define HW_PXP_IRQ (0x000003a0)
1556 #define HW_PXP_IRQ_SET (0x000003a4)
1557 #define HW_PXP_IRQ_CLR (0x000003a8)
1558 #define HW_PXP_IRQ_TOG (0x000003ac)
1560 #define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000
1564 #define BM_PXP_IRQ_RSVD1 0x7FFF0000
1567 #define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000
1570 #define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000
1573 #define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000
1576 #define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000
1579 #define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800
1582 #define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400
1585 #define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200
1588 #define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100
1591 #define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080
1594 #define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040
1597 #define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020
1600 #define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010
1603 #define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008
1606 #define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004
1609 #define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002
1612 #define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001
1614 (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ)
1616 #define HW_PXP_NEXT (0x00000400)
1619 #define BM_PXP_NEXT_POINTER 0xFFFFFFFC
1622 #define BM_PXP_NEXT_RSVD 0x00000002
1625 #define BM_PXP_NEXT_ENABLED 0x00000001
1627 (((v) << 0) & BM_PXP_NEXT_ENABLED)
1629 #define HW_PXP_DEBUGCTRL (0x00000410)
1632 #define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000
1636 #define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00
1639 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0
1640 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1
1641 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2
1642 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4
1643 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8
1644 #define BP_PXP_DEBUGCTRL_SELECT 0
1645 #define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
1647 (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
1648 #define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0
1649 #define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1
1650 #define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2
1651 #define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3
1652 #define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4
1653 #define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5
1654 #define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
1655 #define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7
1656 #define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8
1657 #define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9
1658 #define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10
1659 #define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11
1660 #define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12
1661 #define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13
1662 #define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14
1664 #define HW_PXP_DEBUG (0x00000420)
1666 #define BP_PXP_DEBUG_DATA 0
1667 #define BM_PXP_DEBUG_DATA 0xFFFFFFFF
1670 #define HW_PXP_VERSION (0x00000430)
1673 #define BM_PXP_VERSION_MAJOR 0xFF000000
1677 #define BM_PXP_VERSION_MINOR 0x00FF0000
1680 #define BP_PXP_VERSION_STEP 0
1681 #define BM_PXP_VERSION_STEP 0x0000FFFF
1683 (((v) << 0) & BM_PXP_VERSION_STEP)