Lines Matching +full:0 +full:x001fffff
55 0x0, BIT(0)); in init_rdma()
59 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); in init_rdma()
61 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); in init_rdma()
62 return 0; in init_rdma()
80 MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); in config_rdma_frame()
83 MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); in config_rdma_frame()
90 0x00030071); in config_rdma_frame()
94 0x03C8FE0F); in config_rdma_frame()
101 rdma->ufo_dec_y, 0xFFFFFFFF); in config_rdma_frame()
104 rdma->ufo_dec_c, 0xFFFFFFFF); in config_rdma_frame()
109 rdma->mf_bkgd_in_pxl, 0x001FFFFF); in config_rdma_frame()
113 0x1110); in config_rdma_frame()
115 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0], in config_rdma_frame()
116 0xFFFFFFFF); in config_rdma_frame()
118 0xFFFFFFFF); in config_rdma_frame()
120 0xFFFFFFFF); in config_rdma_frame()
123 rdma->iova_end[0], 0xFFFFFFFF); in config_rdma_frame()
125 rdma->iova_end[1], 0xFFFFFFFF); in config_rdma_frame()
127 rdma->iova_end[2], 0xFFFFFFFF); in config_rdma_frame()
130 rdma->mf_bkgd, 0x001FFFFF); in config_rdma_frame()
132 rdma->sf_bkgd, 0x001FFFFF); in config_rdma_frame()
135 rdma->transform, 0x0F110000); in config_rdma_frame()
137 return 0; in config_rdma_frame()
153 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); in config_rdma_subfrm()
157 subfrm->offset[0], 0xFFFFFFFF); in config_rdma_subfrm()
164 subfrm->offset_0_p, 0xFFFFFFFF); in config_rdma_subfrm()
168 subfrm->offset[1], 0xFFFFFFFF); in config_rdma_subfrm()
171 subfrm->offset[2], 0xFFFFFFFF); in config_rdma_subfrm()
174 0x1FFF1FFF); in config_rdma_subfrm()
177 subfrm->clip, 0x1FFF1FFF); in config_rdma_subfrm()
180 subfrm->clip_ofst, 0x003F001F); in config_rdma_subfrm()
187 return 0; in config_rdma_subfrm()
196 if (ctx->comp->alias_id == 0) in wait_rdma_event()
202 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); in wait_rdma_event()
203 return 0; in wait_rdma_event()
220 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); in init_rsz()
221 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); in init_rsz()
223 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); in init_rsz()
224 return 0; in init_rsz()
237 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); in config_rsz_frame()
238 return 0; in config_rsz_frame()
242 0x03FFFDF3); in config_rsz_frame()
244 0x0FFFC290); in config_rsz_frame()
246 rsz->coeff_step_x, 0x007FFFFF); in config_rsz_frame()
248 rsz->coeff_step_y, 0x007FFFFF); in config_rsz_frame()
249 return 0; in config_rsz_frame()
262 0x00003800); in config_rsz_subfrm()
264 0xFFFFFFFF); in config_rsz_subfrm()
272 csf->luma.left, 0xFFFF); in config_rsz_subfrm()
275 csf->luma.left_subpix, 0x1FFFFF); in config_rsz_subfrm()
277 csf->luma.top, 0xFFFF); in config_rsz_subfrm()
279 csf->luma.top_subpix, 0x1FFFFF); in config_rsz_subfrm()
282 csf->chroma.left, 0xFFFF); in config_rsz_subfrm()
285 csf->chroma.left_subpix, 0x1FFFFF); in config_rsz_subfrm()
288 0xFFFFFFFF); in config_rsz_subfrm()
290 return 0; in config_rsz_subfrm()
304 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, in advance_rsz_subfrm()
308 return 0; in advance_rsz_subfrm()
325 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); in init_wrot()
326 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); in init_wrot()
327 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); in init_wrot()
328 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); in init_wrot()
329 return 0; in init_wrot()
342 MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0], in config_wrot_frame()
343 0xFFFFFFFF); in config_wrot_frame()
345 0xFFFFFFFF); in config_wrot_frame()
347 0xFFFFFFFF); in config_wrot_frame()
350 0xF131510F); in config_wrot_frame()
352 MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0], in config_wrot_frame()
353 0x0000FFFF); in config_wrot_frame()
356 0xFFFF); in config_wrot_frame()
358 0xFFFF); in config_wrot_frame()
360 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, wrot->mat_ctrl, 0xF3); in config_wrot_frame()
362 /* Set the fixed ALPHA as 0xFF */ in config_wrot_frame()
363 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, in config_wrot_frame()
364 0xFF000000); in config_wrot_frame()
368 if (wrot->fifo_test != 0) in config_wrot_frame()
370 wrot->fifo_test, 0xFFF); in config_wrot_frame()
374 wrot->filter, 0x77); in config_wrot_frame()
376 return 0; in config_wrot_frame()
388 subfrm->offset[0], 0x0FFFFFFF); in config_wrot_subfrm()
391 subfrm->offset[1], 0x0FFFFFFF); in config_wrot_subfrm()
394 subfrm->offset[2], 0x0FFFFFFF); in config_wrot_subfrm()
397 0x1FFF1FFF); in config_wrot_subfrm()
400 0x1FFF1FFF); in config_wrot_subfrm()
402 0x1FFF1FFF); in config_wrot_subfrm()
405 subfrm->main_buf, 0x1FFF7F00); in config_wrot_subfrm()
408 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); in config_wrot_subfrm()
410 return 0; in config_wrot_subfrm()
420 if (ctx->comp->alias_id == 0) in wait_wrot_event()
426 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, in wait_wrot_event()
427 0x77); in wait_wrot_event()
430 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); in wait_wrot_event()
432 return 0; in wait_wrot_event()
449 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); in init_wdma()
450 MM_REG_POLL(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0)); in init_wdma()
451 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); in init_wdma()
452 return 0; in init_wdma()
463 MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, in config_wdma_frame()
464 0xFFFFFFFF); in config_wdma_frame()
468 0x0F01B8F0); in config_wdma_frame()
470 MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, wdma->iova[0], in config_wdma_frame()
471 0xFFFFFFFF); in config_wdma_frame()
473 0xFFFFFFFF); in config_wdma_frame()
475 0xFFFFFFFF); in config_wdma_frame()
478 wdma->w_in_byte, 0x0000FFFF); in config_wdma_frame()
481 wdma->uv_stride, 0x0000FFFF); in config_wdma_frame()
482 /* Set the fixed ALPHA as 0xFF */ in config_wdma_frame()
483 MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, in config_wdma_frame()
484 0x800000FF); in config_wdma_frame()
486 return 0; in config_wdma_frame()
498 subfrm->offset[0], 0x0FFFFFFF); in config_wdma_subfrm()
501 subfrm->offset[1], 0x0FFFFFFF); in config_wdma_subfrm()
504 subfrm->offset[2], 0x0FFFFFFF); in config_wdma_subfrm()
507 0x3FFF3FFF); in config_wdma_subfrm()
510 0x3FFF3FFF); in config_wdma_subfrm()
513 0x3FFF3FFF); in config_wdma_subfrm()
516 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); in config_wdma_subfrm()
518 return 0; in config_wdma_subfrm()
528 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); in wait_wdma_event()
529 return 0; in wait_wdma_event()
546 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); in init_ccorr()
548 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); in init_ccorr()
549 return 0; in init_ccorr()
563 (hsize << 16) + (vsize << 0), 0x1FFF1FFF); in config_ccorr_subfrm()
564 return 0; in config_ccorr_subfrm()
587 [MDP_COMP_WPEI] = { MDP_COMP_TYPE_WPEI, 0 },
591 [MDP_COMP_ISP_IMGI] = { MDP_COMP_TYPE_IMGI, 0 },
592 [MDP_COMP_ISP_IMGO] = { MDP_COMP_TYPE_EXTO, 0 },
595 [MDP_COMP_CAMIN] = { MDP_COMP_TYPE_DL_PATH, 0 },
597 [MDP_COMP_RDMA0] = { MDP_COMP_TYPE_RDMA, 0 },
598 [MDP_COMP_CCORR0] = { MDP_COMP_TYPE_CCORR, 0 },
599 [MDP_COMP_RSZ0] = { MDP_COMP_TYPE_RSZ, 0 },
601 [MDP_COMP_PATH0_SOUT] = { MDP_COMP_TYPE_PATH, 0 },
603 [MDP_COMP_WROT0] = { MDP_COMP_TYPE_WROT, 0 },
604 [MDP_COMP_WDMA] = { MDP_COMP_TYPE_WDMA, 0 },
646 [MDP_COMP_RDMA0] = {2, 0, 0},
647 [MDP_COMP_RSZ0] = {1, 0, 0},
648 [MDP_COMP_WROT0] = {1, 0, 0},
649 [MDP_COMP_WDMA] = {1, 0, 0},
650 [MDP_COMP_CCORR0] = {1, 0, 0},
673 for (i = 0; i < ARRAY_SIZE(mdp_comp_matches); i++) in mdp_comp_get_id()
686 if (ret < 0) { in mdp_comp_clock_on()
694 for (i = 0; i < ARRAY_SIZE(comp->clks); i++) { in mdp_comp_clock_on()
707 return 0; in mdp_comp_clock_on()
714 for (i = 0; i < ARRAY_SIZE(comp->clks); i++) { in mdp_comp_clock_off()
728 for (i = 0; i < num; i++) in mdp_comp_clocks_on()
729 if (mdp_comp_clock_on(dev, &comps[i]) != 0) in mdp_comp_clocks_on()
732 return 0; in mdp_comp_clocks_on()
739 for (i = 0; i < num; i++) in mdp_comp_clocks_off()
748 int ret = 0; in mdp_get_subsys_id()
749 int index = 0; in mdp_get_subsys_id()
764 if (ret != 0) { in mdp_get_subsys_id()
772 return 0; in mdp_get_subsys_id()
782 if (of_address_to_resource(node, index, &res) < 0) in __mdp_comp_init()
783 base = 0L; in __mdp_comp_init()
788 comp->regs = of_iomap(node, 0); in __mdp_comp_init()
801 if (id < 0 || id >= MDP_MAX_COMP_COUNT) { in mdp_comp_init()
815 for (i = 0; i < clk_num; i++) { in mdp_comp_init()
844 return 0; in mdp_comp_init()
910 if (id < 0) { in mdp_comp_sub_create()
923 return 0; in mdp_comp_sub_create()
930 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { in mdp_comp_destroy()
947 memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); in mdp_comp_config()
970 if (id < 0) { in mdp_comp_config()
1004 return 0; in mdp_comp_config()
1018 if (param->type < 0 || param->type >= MDP_MAX_COMP_COUNT) { in mdp_comp_ctx_config()
1031 for (i = 0; i < param->num_outputs; i++) in mdp_comp_ctx_config()
1033 return 0; in mdp_comp_ctx_config()