Lines Matching +full:32 +full:mv

92 /* MV Vector Valid */
94 /* MV Flag Valid */
179 /* Current MV Flag Status Pointer for Channel n. (Read only) */
190  * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
578  * Bit[32:30] ch10
611  * Bit[35:32] ch8
623 /* AD_ORIG_WR_PTR[63:32] */
630 /* AD_ORIG_RD_PTR[63:32] */
864  * Bit[2]: MV DSP interrupt
1083  * 0 write 32'haaaa5555 to DDR
1084  * 1 write 32'hffffffff to DDR
1085  * 2 write 32'hha5a55a5a to DDR
1130 /* H264 MV request to DDR enable (default 1) */
1209 /* mv bank0 full status , write "1" to clear */
1211 /* mv bank1 full status , write "1" to clear */
1215 /* mv encode interrupt status; write "1" to clear */
1217 /* mv write memory overflow, write "1" to clear */
1220 /* mv stream length */
1229  * 0 MV is saved in internal DPR
1230  * 1 MV is saved in DDR
1364 /* mv stream crc value, it is calculated in pci module */
1366 /* mv length */
1368 /* mv original crc value */
1370 /* mv original crc value */
1401 /* MV stream base address */
1411 /* Length of 32-bit data burst */
1803  * 2 32kHz setting
1886  * 47:32 Blind detection interrupt for channel 0 ~ 15
1900  * 47:32 Blind detection interrupt for channel 0 ~ 15