130 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc,  in cx88_risc_buffer()  argument
145 	 * estimate risc mem: worst case is one write per page border +  in cx88_risc_buffer()
153 	risc->size = instructions * 8;  in cx88_risc_buffer()
154 	risc->dma = 0;  in cx88_risc_buffer()
155 	risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,  in cx88_risc_buffer()
157 	if (!risc->cpu)  in cx88_risc_buffer()
160 	/* write risc instructions */  in cx88_risc_buffer()
161 	rp = risc->cpu;  in cx88_risc_buffer()
171 	risc->jmp = rp;  in cx88_risc_buffer()
172 	WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);  in cx88_risc_buffer()
177 int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc,  in cx88_risc_databuffer()  argument
185 	 * estimate risc mem: worst case is one write per page border +  in cx88_risc_databuffer()
192 	risc->size = instructions * 8;  in cx88_risc_databuffer()
193 	risc->dma = 0;  in cx88_risc_databuffer()
194 	risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma,  in cx88_risc_databuffer()
196 	if (!risc->cpu)  in cx88_risc_databuffer()
199 	/* write risc instructions */  in cx88_risc_databuffer()
200 	rp = risc->cpu;  in cx88_risc_databuffer()
205 	risc->jmp = rp;  in cx88_risc_databuffer()
206 	WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);  in cx88_risc_databuffer()
216  * we are going to put all thr risc programs into host memory, so we
344 			    unsigned int bpl, u32 risc)  in cx88_sram_channel_setup()  argument
361 	cx_write(ch->cmds_start +  0, risc);  in cx88_sram_channel_setup()
383 static int cx88_risc_decode(u32 risc)  in cx88_risc_decode()  argument
412 	dprintk0("0x%08x [ %s", risc,  in cx88_risc_decode()
413 		 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");  in cx88_risc_decode()
415 		if (risc & (1 << (i + 12)))  in cx88_risc_decode()
417 	pr_cont(" count=%d ]\n", risc & 0xfff);  in cx88_risc_decode()
418 	return incr[risc >> 28] ? incr[risc >> 28] : 1;  in cx88_risc_decode()
425 		"initial risc",  in cx88_sram_channel_dump()
430 		"risc pc",  in cx88_sram_channel_dump()
437 	u32 risc;  in cx88_sram_channel_dump()  local
445 		risc = cx_read(ch->cmds_start + 4 * (i + 11));  in cx88_sram_channel_dump()
446 		pr_cont("  risc%d: ", i);  in cx88_sram_channel_dump()
448 			pr_cont("0x%08x [ arg #%d ]\n", risc, n);  in cx88_sram_channel_dump()
450 			n = cx88_risc_decode(risc);  in cx88_sram_channel_dump()
453 		risc = cx_read(ch->ctrl_start + 4 * i);  in cx88_sram_channel_dump()
455 		n = cx88_risc_decode(risc);  in cx88_sram_channel_dump()
457 			risc = cx_read(ch->ctrl_start + 4 * (i + j));  in cx88_sram_channel_dump()
459 				i + j, risc, j);  in cx88_sram_channel_dump()
537 	/* disable RISC controller + IRQs */  in cx88_shutdown()
568 	cx_write(MO_INT1_STAT,   0xFFFFFFFF); // Clear RISC int  in cx88_reset()
606 	cx_write(MO_INT1_STAT,     0xFFFFFFFF); // Clear RISC int  in cx88_reset()
798 	/* If downstream RISC is enabled, bail out; ALSA is managing DMA */  in cx88_start_audio_dma()
819 	/* If downstream RISC is enabled, bail out; ALSA is managing DMA */  in cx88_stop_audio_dma()