Lines Matching +full:0 +full:x4800
39 #define PCI_DEVICE_ID_COBALT 0x2732
65 #define COBALT_SYSSTAT_DIP0_MSK BIT(0)
98 #define COBALT_I2C_0_BASE 0x0
99 #define COBALT_I2C_1_BASE 0x080
100 #define COBALT_I2C_2_BASE 0x100
101 #define COBALT_I2C_3_BASE 0x180
102 #define COBALT_I2C_HSMA_BASE 0x200
104 #define COBALT_SYS_CTRL_BASE 0x400
114 #define COBALT_SYS_STAT_BASE 0x500
115 #define COBALT_SYS_STAT_MASK (COBALT_SYS_STAT_BASE + 0x08)
116 #define COBALT_SYS_STAT_EDGE (COBALT_SYS_STAT_BASE + 0x0c)
118 #define COBALT_HDL_INFO_BASE 0x4800
119 #define COBALT_HDL_INFO_SIZE 0x200
121 #define COBALT_VID_BASE 0x10000
122 #define COBALT_VID_SIZE 0x1000
127 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
129 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
131 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
133 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
135 (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
137 #define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
139 #define DMA_INTERRUPT_STATUS_REG 0x08
144 #define COBALT_BUS_BAR1_BASE 0x600
145 #define COBALT_BUS_SRAM_BASE 0x0
146 #define COBALT_BUS_CPLD_BASE 0x00600000
147 #define COBALT_BUS_FLASH_BASE 0x08000000
195 #define COBALT_STREAM_FL_DMA_IRQ 0
339 #define ADRS_REG (bar1 + COBALT_BUS_BAR1_BASE + 0)