2  * ths8200 - Texas Instruments THS8200 video encoder driver
23 #include <linux/v4l2-dv-timings.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-device.h>
33 MODULE_PARM_DESC(debug, "debug level (0-2)");
93 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
94  * and then the value-mask (to be OR-ed).
108 	reg->val = ths8200_read(sd, reg->reg & 0xff);  in ths8200_g_register()
109 	reg->size = 1;  in ths8200_g_register()
117 	ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);  in ths8200_s_register()
128 	v4l2_info(sd, "----- Chip status -----\n");  in ths8200_log_status()
129 	v4l2_info(sd, "version: %u\n", state->chip_version);  in ths8200_log_status()
139 	v4l2_print_dv_timings(sd->name, "Configured format:",  in ths8200_log_status()
140 			      &state->dv_timings, true);  in ths8200_log_status()
151 	state->power_on = on;  in ths8200_s_power()
153 	/* Power up/down - leave in reset state until input video is present */  in ths8200_s_power()
168 /* -----------------------------------------------------------------------------
176 	if (enable && !state->power_on)  in ths8200_s_stream()
195 	 * bypass 422-444 interpolation,  in ths8200_core_init()
205 	/**** Display Timing Generator Control, Part 1 (DTG1). ****/  in ths8200_core_init()
207 	/* Disable embedded syncs on the output by setting  in ths8200_core_init()
217 	uint16_t line_start_active_video = (bt->vsync + bt->vbackporch);  in ths8200_setup()
218 	uint16_t line_start_front_porch  = (vtotal(bt) - bt->vfrontporch);  in ths8200_setup()
225 	ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);  in ths8200_setup()
226 	ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);  in ths8200_setup()
229 	if (!bt->interlaced)  in ths8200_setup()
236 		      (bt->hbackporch + bt->hsync) & 0xff);  in ths8200_setup()
237 	/* Zero for SDTV-mode. MSB in 0x2b */  in ths8200_setup()
244 		      ((bt->hbackporch + bt->hsync) & 0x100) >> 1);  in ths8200_setup()
247 	ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);  in ths8200_setup()
249 		      ((bt->hfrontporch) & 0x700) >> 8);  in ths8200_setup()
271 	if (!bt->interlaced)  in ths8200_setup()
274 	/**** Display Timing Generator Control, Part 2 (DTG2). ****/  in ths8200_setup()
277 	 * that sets all the RGB-outputs to zero is used in the blanking areas,  in ths8200_setup()
278 	 * while a line type that enable the RGB-outputs is used in active video  in ths8200_setup()
284 	 * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off.  in ths8200_setup()
286 	 * 0x0 - Active video: Video data is always passed. Used in active  in ths8200_setup()
302 	ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);  in ths8200_setup()
304 			     (bt->hsync >> 2) & 0xc0);  in ths8200_setup()
312 	ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff);  in ths8200_setup()
314 			     ((bt->vsync + 1) >> 2) & 0xc0);  in ths8200_setup()
336 	if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {  in ths8200_setup()
340 	if (bt->polarities & V4L2_DV_VSYNC_POS_POL) {  in ths8200_setup()
346 	/* Timing of video input bus is derived from HS, VS, and FID dedicated  in ths8200_setup()
357 		 polarity, bt->hfrontporch, bt->hbackporch,  in ths8200_setup()
358 		 bt->hsync, bt->vsync);  in ths8200_setup()
370 		return -EINVAL;  in ths8200_s_dv_timings()
375 		return -EINVAL;  in ths8200_s_dv_timings()
378 	timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;  in ths8200_s_dv_timings()
381 	state->dv_timings = *timings;  in ths8200_s_dv_timings()
383 	ths8200_setup(sd, &timings->bt);  in ths8200_s_dv_timings()
395 	*timings = state->dv_timings;  in ths8200_g_dv_timings()
403 	if (timings->pad != 0)  in ths8200_enum_dv_timings()
404 		return -EINVAL;  in ths8200_enum_dv_timings()
413 	if (cap->pad != 0)  in ths8200_dv_timings_cap()
414 		return -EINVAL;  in ths8200_dv_timings_cap()
446 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))  in ths8200_probe()
447 		return -EIO;  in ths8200_probe()
449 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);  in ths8200_probe()
451 		return -ENOMEM;  in ths8200_probe()
453 	sd = &state->sd;  in ths8200_probe()
456 	state->chip_version = ths8200_read(sd, THS8200_VERSION);  in ths8200_probe()
457 	v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);  in ths8200_probe()
461 	error = v4l2_async_register_subdev(&state->sd);  in ths8200_probe()
465 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,  in ths8200_probe()
466 		  client->addr << 1, client->adapter->name);  in ths8200_probe()
476 	v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,  in ths8200_remove()
477 		 client->addr << 1, client->adapter->name);  in ths8200_remove()
480 	v4l2_async_unregister_subdev(&decoder->sd);  in ths8200_remove()