25 #define IMX290_STANDBY 0x3000
26 #define IMX290_REGHOLD 0x3001
27 #define IMX290_XMSTA 0x3002
28 #define IMX290_FR_FDG_SEL 0x3009
29 #define IMX290_BLKLEVEL_LOW 0x300a
30 #define IMX290_BLKLEVEL_HIGH 0x300b
31 #define IMX290_GAIN 0x3014
32 #define IMX290_HMAX_LOW 0x301c
33 #define IMX290_HMAX_HIGH 0x301d
34 #define IMX290_PGCTRL 0x308c
35 #define IMX290_PHY_LANE_NUM 0x3407
36 #define IMX290_CSI_LANE_MODE 0x3443
38 #define IMX290_PGCTRL_REGEN BIT(0)
115 	{ 0x3007, 0x00 },
116 	{ 0x3018, 0x65 },
117 	{ 0x3019, 0x04 },
118 	{ 0x301a, 0x00 },
119 	{ 0x3444, 0x20 },
120 	{ 0x3445, 0x25 },
121 	{ 0x303a, 0x0c },
122 	{ 0x3040, 0x00 },
123 	{ 0x3041, 0x00 },
124 	{ 0x303c, 0x00 },
125 	{ 0x303d, 0x00 },
126 	{ 0x3042, 0x9c },
127 	{ 0x3043, 0x07 },
128 	{ 0x303e, 0x49 },
129 	{ 0x303f, 0x04 },
130 	{ 0x304b, 0x0a },
131 	{ 0x300f, 0x00 },
132 	{ 0x3010, 0x21 },
133 	{ 0x3012, 0x64 },
134 	{ 0x3016, 0x09 },
135 	{ 0x3070, 0x02 },
136 	{ 0x3071, 0x11 },
137 	{ 0x309b, 0x10 },
138 	{ 0x309c, 0x22 },
139 	{ 0x30a2, 0x02 },
140 	{ 0x30a6, 0x20 },
141 	{ 0x30a8, 0x20 },
142 	{ 0x30aa, 0x20 },
143 	{ 0x30ac, 0x20 },
144 	{ 0x30b0, 0x43 },
145 	{ 0x3119, 0x9e },
146 	{ 0x311c, 0x1e },
147 	{ 0x311e, 0x08 },
148 	{ 0x3128, 0x05 },
149 	{ 0x313d, 0x83 },
150 	{ 0x3150, 0x03 },
151 	{ 0x317e, 0x00 },
152 	{ 0x32b8, 0x50 },
153 	{ 0x32b9, 0x10 },
154 	{ 0x32ba, 0x00 },
155 	{ 0x32bb, 0x04 },
156 	{ 0x32c8, 0x50 },
157 	{ 0x32c9, 0x10 },
158 	{ 0x32ca, 0x00 },
159 	{ 0x32cb, 0x04 },
160 	{ 0x332c, 0xd3 },
161 	{ 0x332d, 0x10 },
162 	{ 0x332e, 0x0d },
163 	{ 0x3358, 0x06 },
164 	{ 0x3359, 0xe1 },
165 	{ 0x335a, 0x11 },
166 	{ 0x3360, 0x1e },
167 	{ 0x3361, 0x61 },
168 	{ 0x3362, 0x10 },
169 	{ 0x33b0, 0x50 },
170 	{ 0x33b2, 0x1a },
171 	{ 0x33b3, 0x04 },
176 	{ 0x3007, 0x00 },
177 	{ 0x303a, 0x0c },
178 	{ 0x3414, 0x0a },
179 	{ 0x3472, 0x80 },
180 	{ 0x3473, 0x07 },
181 	{ 0x3418, 0x38 },
182 	{ 0x3419, 0x04 },
183 	{ 0x3012, 0x64 },
184 	{ 0x3013, 0x00 },
185 	{ 0x305c, 0x18 },
186 	{ 0x305d, 0x03 },
187 	{ 0x305e, 0x20 },
188 	{ 0x305f, 0x01 },
189 	{ 0x315e, 0x1a },
190 	{ 0x3164, 0x1a },
191 	{ 0x3480, 0x49 },
193 	{ 0x3405, 0x10 },
194 	{ 0x3446, 0x57 },
195 	{ 0x3447, 0x00 },
196 	{ 0x3448, 0x37 },
197 	{ 0x3449, 0x00 },
198 	{ 0x344a, 0x1f },
199 	{ 0x344b, 0x00 },
200 	{ 0x344c, 0x1f },
201 	{ 0x344d, 0x00 },
202 	{ 0x344e, 0x1f },
203 	{ 0x344f, 0x00 },
204 	{ 0x3450, 0x77 },
205 	{ 0x3451, 0x00 },
206 	{ 0x3452, 0x1f },
207 	{ 0x3453, 0x00 },
208 	{ 0x3454, 0x17 },
209 	{ 0x3455, 0x00 },
214 	{ 0x3007, 0x10 },
215 	{ 0x303a, 0x06 },
216 	{ 0x3414, 0x04 },
217 	{ 0x3472, 0x00 },
218 	{ 0x3473, 0x05 },
219 	{ 0x3418, 0xd0 },
220 	{ 0x3419, 0x02 },
221 	{ 0x3012, 0x64 },
222 	{ 0x3013, 0x00 },
223 	{ 0x305c, 0x20 },
224 	{ 0x305d, 0x00 },
225 	{ 0x305e, 0x20 },
226 	{ 0x305f, 0x01 },
227 	{ 0x315e, 0x1a },
228 	{ 0x3164, 0x1a },
229 	{ 0x3480, 0x49 },
231 	{ 0x3405, 0x10 },
232 	{ 0x3446, 0x4f },
233 	{ 0x3447, 0x00 },
234 	{ 0x3448, 0x2f },
235 	{ 0x3449, 0x00 },
236 	{ 0x344a, 0x17 },
237 	{ 0x344b, 0x00 },
238 	{ 0x344c, 0x17 },
239 	{ 0x344d, 0x00 },
240 	{ 0x344e, 0x17 },
241 	{ 0x344f, 0x00 },
242 	{ 0x3450, 0x57 },
243 	{ 0x3451, 0x00 },
244 	{ 0x3452, 0x17 },
245 	{ 0x3453, 0x00 },
246 	{ 0x3454, 0x17 },
247 	{ 0x3455, 0x00 },
251 	{ 0x3005, 0x00},
252 	{ 0x3046, 0x00},
253 	{ 0x3129, 0x1d},
254 	{ 0x317c, 0x12},
255 	{ 0x31ec, 0x37},
256 	{ 0x3441, 0x0a},
257 	{ 0x3442, 0x0a},
258 	{ 0x300a, 0x3c},
259 	{ 0x300b, 0x00},
263 	{ 0x3005, 0x01 },
264 	{ 0x3046, 0x01 },
265 	{ 0x3129, 0x00 },
266 	{ 0x317c, 0x00 },
267 	{ 0x31ec, 0x0e },
268 	{ 0x3441, 0x0c },
269 	{ 0x3442, 0x0c },
270 	{ 0x300a, 0xf0 },
271 	{ 0x300b, 0x00 },
275 #define FREQ_INDEX_1080P	0
311 		.hmax = 0x1130,
319 		.hmax = 0x19c8,
330 		.hmax = 0x0898,
338 		.hmax = 0x0ce4,
377 	*value = regval & 0xff;  in imx290_read_reg()
379 	return 0;  in imx290_read_reg()
402 	for (i = 0; i < num_settings; ++i, ++settings) {  in imx290_set_register_array()
404 		if (ret < 0)  in imx290_set_register_array()
411 	return 0;  in imx290_set_register_array()
420 	ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x01);  in imx290_write_buffered_reg()
426 	for (i = 0; i < nr_regs; i++) {  in imx290_write_buffered_reg()
435 	ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x00);  in imx290_write_buffered_reg()
460 	ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);  in imx290_stop_streaming()
461 	if (ret < 0)  in imx290_stop_streaming()
466 	return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);  in imx290_stop_streaming()
473 	int ret = 0;  in imx290_set_ctrl()
477 		return 0;  in imx290_set_ctrl()
485 			imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);  in imx290_set_ctrl()
486 			imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);  in imx290_set_ctrl()
493 			imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);  in imx290_set_ctrl()
497 						 0x3c);  in imx290_set_ctrl()
500 						 0xf0);  in imx290_set_ctrl()
501 			imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);  in imx290_set_ctrl()
527 	return 0;  in imx290_enum_mbus_code()
537 	if ((fse->code != imx290_formats[0].code) &&  in imx290_enum_frame_size()
549 	return 0;  in imx290_enum_frame_size()
571 	return 0;  in imx290_get_fmt()
616 	for (i = 0; i < ARRAY_SIZE(imx290_formats); i++)  in imx290_set_fmt()
621 		i = 0;  in imx290_set_fmt()
645 	return 0;  in imx290_set_fmt()
651 	struct v4l2_subdev_format fmt = { 0 };  in imx290_entity_init_cfg()
659 	return 0;  in imx290_entity_init_cfg()
671 		if (ret < 0) {  in imx290_write_current_format()
680 		if (ret < 0) {  in imx290_write_current_format()
690 	return 0;  in imx290_write_current_format()
697 	ret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (val & 0xff));  in imx290_set_hmax()
703 	ret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((val >> 8) & 0xff));  in imx290_set_hmax()
709 	return 0;  in imx290_set_hmax()
721 	if (ret < 0) {  in imx290_start_streaming()
728 	if (ret < 0) {  in imx290_start_streaming()
736 	if (ret < 0) {  in imx290_start_streaming()
741 	if (ret < 0)  in imx290_start_streaming()
751 	ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);  in imx290_start_streaming()
752 	if (ret < 0)  in imx290_start_streaming()
758 	return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);  in imx290_start_streaming()
764 	int ret = 0;  in imx290_set_stream()
768 		if (ret < 0)  in imx290_set_stream()
791 	for (i = 0; i < IMX290_NUM_SUPPLIES; i++)  in imx290_get_regulators()
800 	int ret = 0, laneval, frsel;  in imx290_set_data_lanes()
804 		laneval = 0x01;  in imx290_set_data_lanes()
805 		frsel = 0x02;  in imx290_set_data_lanes()
808 		laneval = 0x03;  in imx290_set_data_lanes()
809 		frsel = 0x01;  in imx290_set_data_lanes()
861 	gpiod_set_value_cansleep(imx290->rst_gpio, 0);  in imx290_power_on()
867 	return 0;  in imx290_power_on()
879 	return 0;  in imx290_power_off()
908  * Returns 0 if all link frequencies used by the driver for the given number
919 	for (i = 0; i < freqs_count; i++) {  in imx290_check_link_freqs()
920 		for (j = 0; j < ep->nr_of_link_frequencies; j++)  in imx290_check_link_freqs()
926 	return 0;  in imx290_check_link_freqs()
1023 	if (ret < 0) {  in imx290_probe()
1048 			  V4L2_CID_GAIN, 0, 72, 1, 0);  in imx290_probe()
1053 				       imx290_link_freqs_num(imx290) - 1, 0,  in imx290_probe()
1066 				     0, 0, imx290_test_pattern_menu);  in imx290_probe()
1085 	if (ret < 0) {  in imx290_probe()
1091 	if (ret < 0) {  in imx290_probe()
1098 	if (ret < 0) {  in imx290_probe()
1109 	return 0;  in imx290_probe()