Lines Matching refs:sdp_io_write
419 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in sdp_io_write() function
428 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); in sdp_io_write_and_or()
923 sdp_io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
1748 sdp_io_write(sd, 0xe1, c->A1); in sdp_csc_coeff()
1750 sdp_io_write(sd, 0xe3, c->A2); in sdp_csc_coeff()
1752 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
1756 sdp_io_write(sd, 0xe7, c->A4); in sdp_csc_coeff()
1760 sdp_io_write(sd, 0xe9, c->B1); in sdp_csc_coeff()
1762 sdp_io_write(sd, 0xeb, c->B2); in sdp_csc_coeff()
1764 sdp_io_write(sd, 0xed, c->B3); in sdp_csc_coeff()
1768 sdp_io_write(sd, 0xef, c->B4); in sdp_csc_coeff()
1772 sdp_io_write(sd, 0xf1, c->C1); in sdp_csc_coeff()
1774 sdp_io_write(sd, 0xf3, c->C2); in sdp_csc_coeff()
1776 sdp_io_write(sd, 0xf5, c->C3); in sdp_csc_coeff()
1780 sdp_io_write(sd, 0xf7, c->C4); in sdp_csc_coeff()
1813 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ in select_input()
1814 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ in select_input()
1826 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ in select_input()
2910 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2911 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); in adv7842_s_sdp_io()
2912 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); in adv7842_s_sdp_io()
2913 sdp_io_write(sd, 0x97, s->hs_width & 0xff); in adv7842_s_sdp_io()
2914 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2915 sdp_io_write(sd, 0x99, s->de_beg & 0xff); in adv7842_s_sdp_io()
2916 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); in adv7842_s_sdp_io()
2917 sdp_io_write(sd, 0x9b, s->de_end & 0xff); in adv7842_s_sdp_io()
2918 sdp_io_write(sd, 0xa8, s->vs_beg_o); in adv7842_s_sdp_io()
2919 sdp_io_write(sd, 0xa9, s->vs_beg_e); in adv7842_s_sdp_io()
2920 sdp_io_write(sd, 0xaa, s->vs_end_o); in adv7842_s_sdp_io()
2921 sdp_io_write(sd, 0xab, s->vs_end_e); in adv7842_s_sdp_io()
2922 sdp_io_write(sd, 0xac, s->de_v_beg_o); in adv7842_s_sdp_io()
2923 sdp_io_write(sd, 0xad, s->de_v_beg_e); in adv7842_s_sdp_io()
2924 sdp_io_write(sd, 0xae, s->de_v_end_o); in adv7842_s_sdp_io()
2925 sdp_io_write(sd, 0xaf, s->de_v_end_e); in adv7842_s_sdp_io()
2928 sdp_io_write(sd, 0x94, 0x00); in adv7842_s_sdp_io()
2929 sdp_io_write(sd, 0x95, 0x00); in adv7842_s_sdp_io()
2930 sdp_io_write(sd, 0x96, 0x00); in adv7842_s_sdp_io()
2931 sdp_io_write(sd, 0x97, 0x20); in adv7842_s_sdp_io()
2932 sdp_io_write(sd, 0x98, 0x00); in adv7842_s_sdp_io()
2933 sdp_io_write(sd, 0x99, 0x00); in adv7842_s_sdp_io()
2934 sdp_io_write(sd, 0x9a, 0x00); in adv7842_s_sdp_io()
2935 sdp_io_write(sd, 0x9b, 0x00); in adv7842_s_sdp_io()
2936 sdp_io_write(sd, 0xa8, 0x04); in adv7842_s_sdp_io()
2937 sdp_io_write(sd, 0xa9, 0x04); in adv7842_s_sdp_io()
2938 sdp_io_write(sd, 0xaa, 0x04); in adv7842_s_sdp_io()
2939 sdp_io_write(sd, 0xab, 0x04); in adv7842_s_sdp_io()
2940 sdp_io_write(sd, 0xac, 0x04); in adv7842_s_sdp_io()
2941 sdp_io_write(sd, 0xad, 0x04); in adv7842_s_sdp_io()
2942 sdp_io_write(sd, 0xae, 0x04); in adv7842_s_sdp_io()
2943 sdp_io_write(sd, 0xaf, 0x04); in adv7842_s_sdp_io()
3048 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ in adv7842_core_init()
3049 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ in adv7842_core_init()
3050 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
3051 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
3052 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
3054 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ in adv7842_core_init()
3055 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ in adv7842_core_init()
3056 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, in adv7842_core_init()
3058 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ in adv7842_core_init()
3059 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ in adv7842_core_init()
3060 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ in adv7842_core_init()
3061 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ in adv7842_core_init()
3068 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ in adv7842_core_init()
3128 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3129 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3130 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3131 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3132 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3133 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3134 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3135 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3136 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3137 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ in adv7842_ddr_ram_test()
3141 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ in adv7842_ddr_ram_test()