43 	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };  in stv0297_writereg()
48 		dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",  in stv0297_writereg()
51 	return (ret != 1) ? -1 : 0;  in stv0297_writereg()
58 	u8 b1[] = { 0 };  in stv0297_readreg()
59 	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},  in stv0297_readreg()
65 		if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {  in stv0297_readreg()
66 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);  in stv0297_readreg()
70 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);  in stv0297_readreg()
75 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);  in stv0297_readreg()
80 	return b1[0];  in stv0297_readreg()
92 	return 0;  in stv0297_writereg_mask()
98 	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =  in stv0297_readregs()
105 		if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {  in stv0297_readregs()
106 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);  in stv0297_readregs()
110 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);  in stv0297_readregs()
115 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);  in stv0297_readregs()
120 	return 0;  in stv0297_readregs()
127 	tmp = (u64)(stv0297_readreg(state, 0x55)  in stv0297_get_symbolrate()
128 		    | (stv0297_readreg(state, 0x56) << 8)  in stv0297_get_symbolrate()
129 		    | (stv0297_readreg(state, 0x57) << 16)  in stv0297_get_symbolrate()
130 		    | (stv0297_readreg(state, 0x58) << 24));  in stv0297_get_symbolrate()
146 	stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));  in stv0297_set_symbolrate()
147 	stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));  in stv0297_set_symbolrate()
148 	stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));  in stv0297_set_symbolrate()
149 	stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));  in stv0297_set_symbolrate()
161 	if (tmp >= 0) {  in stv0297_set_sweeprate()
168 	stv0297_writereg(state, 0x60, tmp & 0xFF);  in stv0297_set_sweeprate()
169 	stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);  in stv0297_set_sweeprate()
178 	if (tmp < 0)  in stv0297_set_carrieroffset()
179 		tmp += 0x10000000;  in stv0297_set_carrieroffset()
180 	tmp &= 0x0FFFFFFF;  in stv0297_set_carrieroffset()
182 	stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));  in stv0297_set_carrieroffset()
183 	stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));  in stv0297_set_carrieroffset()
184 	stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));  in stv0297_set_carrieroffset()
185 	stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);  in stv0297_set_carrieroffset()
193 	stv0297_writereg(state, 0x6B, 0x00);
195 	tmp = stv0297_readreg(state, 0x66);
196 	tmp |= (stv0297_readreg(state, 0x67) << 8);
197 	tmp |= (stv0297_readreg(state, 0x68) << 16);
198 	tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
216 	if (tmp > 0xffff)  in stv0297_set_initialdemodfreq()
217 		tmp = 0xffff;  in stv0297_set_initialdemodfreq()
219 	stv0297_writereg_mask(state, 0x25, 0x80, 0x80);  in stv0297_set_initialdemodfreq()
220 	stv0297_writereg(state, 0x21, tmp >> 8);  in stv0297_set_initialdemodfreq()
221 	stv0297_writereg(state, 0x20, tmp);  in stv0297_set_initialdemodfreq()
227 	int val = 0;  in stv0297_set_qam()
231 		val = 0;  in stv0297_set_qam()
254 	stv0297_writereg_mask(state, 0x00, 0x70, val << 4);  in stv0297_set_qam()
256 	return 0;  in stv0297_set_qam()
262 	int val = 0;  in stv0297_set_inversion()
266 		val = 0;  in stv0297_set_inversion()
277 	stv0297_writereg_mask(state, 0x83, 0x08, val << 3);  in stv0297_set_inversion()
279 	return 0;  in stv0297_set_inversion()
287 		stv0297_writereg(state, 0x87, 0x78);  in stv0297_i2c_gate_ctrl()
288 		stv0297_writereg(state, 0x86, 0xc8);  in stv0297_i2c_gate_ctrl()
291 	return 0;  in stv0297_i2c_gate_ctrl()
300 	for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)  in stv0297_init()
304 	state->last_ber = 0;  in stv0297_init()
306 	return 0;  in stv0297_init()
313 	stv0297_writereg_mask(state, 0x80, 1, 1);  in stv0297_sleep()
315 	return 0;  in stv0297_sleep()
323 	u8 sync = stv0297_readreg(state, 0xDF);  in stv0297_read_status()
325 	*status = 0;  in stv0297_read_status()
326 	if (sync & 0x80)  in stv0297_read_status()
329 	return 0;  in stv0297_read_status()
337 	stv0297_readregs(state, 0xA0, BER, 3);  in stv0297_read_ber()
338 	if (!(BER[0] & 0x80)) {  in stv0297_read_ber()
340 		stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);  in stv0297_read_ber()
345 	return 0;  in stv0297_read_ber()
355 	stv0297_readregs(state, 0x41, STRENGTH, 3);  in stv0297_read_signal_strength()
356 	tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];  in stv0297_read_signal_strength()
357 	if (STRENGTH[2] & 0x20) {  in stv0297_read_signal_strength()
358 		if (tmp < 0x200)  in stv0297_read_signal_strength()
359 			tmp = 0;  in stv0297_read_signal_strength()
361 			tmp = tmp - 0x200;  in stv0297_read_signal_strength()
363 		if (tmp > 0x1ff)  in stv0297_read_signal_strength()
364 			tmp = 0;  in stv0297_read_signal_strength()
366 			tmp = 0x1ff - tmp;  in stv0297_read_signal_strength()
369 	return 0;  in stv0297_read_signal_strength()
377 	stv0297_readregs(state, 0x07, SNR, 2);  in stv0297_read_snr()
378 	*snr = SNR[1] << 8 | SNR[0];  in stv0297_read_snr()
380 	return 0;  in stv0297_read_snr()
387 	stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */  in stv0297_read_ucblocks()
389 	*ucblocks = (stv0297_readreg(state, 0xD5) << 8)  in stv0297_read_ucblocks()
390 		| stv0297_readreg(state, 0xD4);  in stv0297_read_ucblocks()
392 	stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */  in stv0297_read_ucblocks()
393 	stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */  in stv0297_read_ucblocks()
395 	return 0;  in stv0297_read_ucblocks()
450 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);  in stv0297_set_frontend()
454 	stv0297_writereg(state, 0x82, 0x0);  in stv0297_set_frontend()
460 	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);  in stv0297_set_frontend()
461 	stv0297_writereg(state, 0x41, 0x00);  in stv0297_set_frontend()
462 	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);  in stv0297_set_frontend()
463 	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);  in stv0297_set_frontend()
464 	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);  in stv0297_set_frontend()
465 	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);  in stv0297_set_frontend()
466 	stv0297_writereg(state, 0x72, 0x00);  in stv0297_set_frontend()
467 	stv0297_writereg(state, 0x73, 0x00);  in stv0297_set_frontend()
468 	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);  in stv0297_set_frontend()
469 	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);  in stv0297_set_frontend()
470 	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);  in stv0297_set_frontend()
473 	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);  in stv0297_set_frontend()
474 	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);  in stv0297_set_frontend()
475 	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);  in stv0297_set_frontend()
476 	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);  in stv0297_set_frontend()
477 	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);  in stv0297_set_frontend()
480 	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);  in stv0297_set_frontend()
483 	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);  in stv0297_set_frontend()
484 	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);  in stv0297_set_frontend()
487 	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);  in stv0297_set_frontend()
488 	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);  in stv0297_set_frontend()
491 	u_threshold = stv0297_readreg(state, 0x00) & 0xf;  in stv0297_set_frontend()
492 	initial_u = stv0297_readreg(state, 0x01) >> 4;  in stv0297_set_frontend()
493 	blind_u = stv0297_readreg(state, 0x01) & 0xf;  in stv0297_set_frontend()
494 	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);  in stv0297_set_frontend()
495 	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);  in stv0297_set_frontend()
496 	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);  in stv0297_set_frontend()
497 	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);  in stv0297_set_frontend()
498 	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);  in stv0297_set_frontend()
501 	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);  in stv0297_set_frontend()
504 	stv0297_writereg(state, 0x63, 0x00);  in stv0297_set_frontend()
505 	stv0297_writereg(state, 0x64, 0x00);  in stv0297_set_frontend()
506 	stv0297_writereg(state, 0x65, 0x00);  in stv0297_set_frontend()
507 	stv0297_writereg(state, 0x66, 0x00);  in stv0297_set_frontend()
508 	stv0297_writereg(state, 0x67, 0x00);  in stv0297_set_frontend()
509 	stv0297_writereg(state, 0x68, 0x00);  in stv0297_set_frontend()
510 	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);  in stv0297_set_frontend()
523 		stv0297_writereg_mask(state, 0x88, 0x08, 0x00);  in stv0297_set_frontend()
525 		stv0297_writereg_mask(state, 0x88, 0x08, 0x08);  in stv0297_set_frontend()
527 	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);  in stv0297_set_frontend()
528 	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);  in stv0297_set_frontend()
529 	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);  in stv0297_set_frontend()
530 	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);  in stv0297_set_frontend()
531 	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);  in stv0297_set_frontend()
532 	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);  in stv0297_set_frontend()
533 	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);  in stv0297_set_frontend()
539 		if (stv0297_readreg(state, 0x43) & 0x08)  in stv0297_set_frontend()
552 		if (stv0297_readreg(state, 0x82) & 0x04) {  in stv0297_set_frontend()
565 		if (stv0297_readreg(state, 0x82) & 0x08) {  in stv0297_set_frontend()
574 	stv0297_writereg_mask(state, 0x6a, 1, 0);  in stv0297_set_frontend()
575 	stv0297_writereg_mask(state, 0x88, 8, 0);  in stv0297_set_frontend()
582 		if (stv0297_readreg(state, 0xDF) & 0x80) {  in stv0297_set_frontend()
592 	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {  in stv0297_set_frontend()
597 	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);  in stv0297_set_frontend()
599 	return 0;  in stv0297_set_frontend()
602 	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);  in stv0297_set_frontend()
603 	return 0;  in stv0297_set_frontend()
612 	reg_00 = stv0297_readreg(state, 0x00);  in stv0297_get_frontend()
613 	reg_83 = stv0297_readreg(state, 0x83);  in stv0297_get_frontend()
616 	p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;  in stv0297_get_frontend()
622 	switch ((reg_00 >> 4) & 0x7) {  in stv0297_get_frontend()
623 	case 0:  in stv0297_get_frontend()
640 	return 0;  in stv0297_get_frontend()
664 	state->last_ber = 0;  in stv0297_attach()
665 	state->base_freq = 0;  in stv0297_attach()
668 	if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)  in stv0297_attach()