38 	} while (0)
42 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len };  in i2c_writebytes()
51 	return 0;  in i2c_writebytes()
56 	u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff };  in sp887x_writereg()
57 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 };  in sp887x_writereg()
64 		if (!(reg == 0xf1a && data == 0x000 &&  in sp887x_writereg()
68 			       __func__, reg & 0xffff, data & 0xffff, ret);  in sp887x_writereg()
73 	return 0;  in sp887x_writereg()
78 	u8 b0 [] = { reg >> 8 , reg & 0xff };  in sp887x_readreg()
81 	struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },  in sp887x_readreg()
89 	return (((b1[0] << 8) | b1[1]) & 0xfff);  in sp887x_readreg()
95 	sp887x_writereg(state, 0xf08, 0x000);  in sp887x_microcontroller_stop()
96 	sp887x_writereg(state, 0xf09, 0x000);  in sp887x_microcontroller_stop()
99 	sp887x_writereg(state, 0xf00, 0x000);  in sp887x_microcontroller_stop()
105 	sp887x_writereg(state, 0xf08, 0x000);  in sp887x_microcontroller_start()
106 	sp887x_writereg(state, 0xf09, 0x000);  in sp887x_microcontroller_start()
109 	sp887x_writereg(state, 0xf00, 0x001);  in sp887x_microcontroller_start()
116 	sp887x_writereg(state, 0x33c, 0x054);  in sp887x_setup_agc()
117 	sp887x_writereg(state, 0x33b, 0x04c);  in sp887x_setup_agc()
118 	sp887x_writereg(state, 0x328, 0x000);  in sp887x_setup_agc()
119 	sp887x_writereg(state, 0x327, 0x005);  in sp887x_setup_agc()
120 	sp887x_writereg(state, 0x326, 0x001);  in sp887x_setup_agc()
121 	sp887x_writereg(state, 0x325, 0x001);  in sp887x_setup_agc()
122 	sp887x_writereg(state, 0x324, 0x001);  in sp887x_setup_agc()
123 	sp887x_writereg(state, 0x318, 0x050);  in sp887x_setup_agc()
124 	sp887x_writereg(state, 0x317, 0x3fe);  in sp887x_setup_agc()
125 	sp887x_writereg(state, 0x316, 0x001);  in sp887x_setup_agc()
126 	sp887x_writereg(state, 0x313, 0x005);  in sp887x_setup_agc()
127 	sp887x_writereg(state, 0x312, 0x002);  in sp887x_setup_agc()
128 	sp887x_writereg(state, 0x306, 0x000);  in sp887x_setup_agc()
129 	sp887x_writereg(state, 0x303, 0x000);  in sp887x_setup_agc()
133 #define FW_SIZE 0x4000
147 	/* ignore the first 10 bytes, then we expect 0x4000 bytes of firmware */  in sp887x_initial_setup()
152 	sp887x_writereg(state, 0xf1a, 0x000);  in sp887x_initial_setup()
159 	/* bit 0x8000 in address is set to enable 13bit mode */  in sp887x_initial_setup()
160 	sp887x_writereg(state, 0x8f08, 0x1fff);  in sp887x_initial_setup()
163 	sp887x_writereg(state, 0x8f0a, 0x0000);  in sp887x_initial_setup()
165 	for (i = 0; i < FW_SIZE; i += BLOCKSIZE) {  in sp887x_initial_setup()
172 		/* bit 0x8000 in address is set to enable 13bit mode */  in sp887x_initial_setup()
173 		/* bit 0x4000 enables multibyte read/write transfers */  in sp887x_initial_setup()
174 		/* write register is 0xf0a */  in sp887x_initial_setup()
175 		buf[0] = 0xcf;  in sp887x_initial_setup()
176 		buf[1] = 0x0a;  in sp887x_initial_setup()
180 		if ((err = i2c_writebytes (state, buf, c+2)) < 0) {  in sp887x_initial_setup()
188 	sp887x_writereg(state, 0xc13, 0x001);  in sp887x_initial_setup()
191 	sp887x_writereg(state, 0xc14, 0x000);  in sp887x_initial_setup()
194 	sp887x_writereg(state, 0xc1a, 0x872);  in sp887x_initial_setup()
195 	sp887x_writereg(state, 0xc1b, 0x001);  in sp887x_initial_setup()
196 	sp887x_writereg(state, 0xc1c, 0x000); /* parallel mode (serial mode == 1) */  in sp887x_initial_setup()
197 	sp887x_writereg(state, 0xc1a, 0x871);  in sp887x_initial_setup()
200 	sp887x_writereg(state, 0x301, 0x002);  in sp887x_initial_setup()
204 	/* bit 0x010: enable data valid signal */  in sp887x_initial_setup()
205 	sp887x_writereg(state, 0xd00, 0x010);  in sp887x_initial_setup()
206 	sp887x_writereg(state, 0x0d1, 0x000);  in sp887x_initial_setup()
207 	return 0;  in sp887x_initial_setup()
214 	*reg0xc05 = 0x000;  in configure_reg0xc05()
226 		known_parameters = 0;  in configure_reg0xc05()
245 		known_parameters = 0;  in configure_reg0xc05()
267 		known_parameters = 0;  in configure_reg0xc05()
278 	return 0;  in configure_reg0xc05()
318 		bw_index = 0;  in sp887x_correct_offsets()
339 	sp887x_writereg(state, 0x319, srate_correction[bw_index] >> 12);  in sp887x_correct_offsets()
340 	sp887x_writereg(state, 0x31a, srate_correction[bw_index] & 0xfff);  in sp887x_correct_offsets()
343 	sp887x_writereg(state, 0x309, frequency_shift >> 12);  in sp887x_correct_offsets()
344 	sp887x_writereg(state, 0x30a, frequency_shift & 0xfff);  in sp887x_correct_offsets()
368 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);  in sp887x_setup_frontend_parameters()
372 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);  in sp887x_setup_frontend_parameters()
378 	sp887x_readreg(state, 0x200);  in sp887x_setup_frontend_parameters()
388 		val = 0;  in sp887x_setup_frontend_parameters()
390 	sp887x_writereg(state, 0x311, val);  in sp887x_setup_frontend_parameters()
392 	/* scan order: 2k first = 0, 8k first = 1 */  in sp887x_setup_frontend_parameters()
394 		sp887x_writereg(state, 0x338, 0x000);  in sp887x_setup_frontend_parameters()
396 		sp887x_writereg(state, 0x338, 0x001);  in sp887x_setup_frontend_parameters()
398 	sp887x_writereg(state, 0xc05, reg0xc05);  in sp887x_setup_frontend_parameters()
405 		val = 0 << 3;  in sp887x_setup_frontend_parameters()
407 	/* enable OFDM and SAW bits as lock indicators in sync register 0xf17,  in sp887x_setup_frontend_parameters()
410 	sp887x_writereg(state, 0xf14, 0x160 | val);  in sp887x_setup_frontend_parameters()
411 	sp887x_writereg(state, 0xf15, 0x000);  in sp887x_setup_frontend_parameters()
414 	return 0;  in sp887x_setup_frontend_parameters()
420 	u16 snr12 = sp887x_readreg(state, 0xf16);  in sp887x_read_status()
421 	u16 sync0x200 = sp887x_readreg(state, 0x200);  in sp887x_read_status()
422 	u16 sync0xf17 = sp887x_readreg(state, 0xf17);  in sp887x_read_status()
424 	*status = 0;  in sp887x_read_status()
426 	if (snr12 > 0x00f)  in sp887x_read_status()
429 	//if (sync0x200 & 0x004)  in sp887x_read_status()
432 	//if (sync0x200 & 0x008)  in sp887x_read_status()
435 	if ((sync0xf17 & 0x00f) == 0x002) {  in sp887x_read_status()
440 	if (sync0x200 & 0x001) {	/* tuner adjustment requested...*/  in sp887x_read_status()
441 		int steps = (sync0x200 >> 4) & 0x00f;  in sp887x_read_status()
442 		if (steps & 0x008)  in sp887x_read_status()
448 	return 0;  in sp887x_read_status()
455 	*ber = (sp887x_readreg(state, 0xc08) & 0x3f) |  in sp887x_read_ber()
456 	       (sp887x_readreg(state, 0xc07) << 6);  in sp887x_read_ber()
457 	sp887x_writereg(state, 0xc08, 0x000);  in sp887x_read_ber()
458 	sp887x_writereg(state, 0xc07, 0x000);  in sp887x_read_ber()
459 	if (*ber >= 0x3fff0)  in sp887x_read_ber()
460 		*ber = ~0;  in sp887x_read_ber()
462 	return 0;  in sp887x_read_ber()
469 	u16 snr12 = sp887x_readreg(state, 0xf16);  in sp887x_read_signal_strength()
471 	*strength = (signal < 0xffff) ? signal : 0xffff;  in sp887x_read_signal_strength()
473 	return 0;  in sp887x_read_signal_strength()
480 	u16 snr12 = sp887x_readreg(state, 0xf16);  in sp887x_read_snr()
483 	return 0;  in sp887x_read_snr()
490 	*ucblocks = sp887x_readreg(state, 0xc0c);  in sp887x_read_ucblocks()
491 	if (*ucblocks == 0xfff)  in sp887x_read_ucblocks()
492 		*ucblocks = ~0;  in sp887x_read_ucblocks()
494 	return 0;  in sp887x_read_ucblocks()
502 		return sp887x_writereg(state, 0x206, 0x001);  in sp887x_i2c_gate_ctrl()
504 		return sp887x_writereg(state, 0x206, 0x000);  in sp887x_i2c_gate_ctrl()
513 	sp887x_writereg(state, 0xc18, 0x000);  in sp887x_sleep()
515 	return 0;  in sp887x_sleep()
544 	sp887x_writereg(state, 0xc18, 0x00d);  in sp887x_init()
546 	return 0;  in sp887x_init()
554 	return 0;  in sp887x_get_tune_settings()
577 	state->initialised = 0;  in sp887x_attach()
580 	if (sp887x_readreg(state, 0x0200) < 0) goto error;  in sp887x_attach()