Lines Matching +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
10 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
126 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; in i2c_write()
135 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; in i2c_read()
138 static int i2cread(struct mxl *state, u8 *data, int len) in i2cread() argument
140 return i2c_read(state->base->i2c, state->base->adr, data, len); in i2cread()
143 static int i2cwrite(struct mxl *state, u8 *data, int len) in i2cwrite() argument
145 return i2c_write(state->base->i2c, state->base->adr, data, len); in i2cwrite()
148 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) in read_register_unlocked() argument
157 stat = i2cwrite(state, data, in read_register_unlocked()
160 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register_unlocked()
162 stat = i2cread(state, (u8 *) val, in read_register_unlocked()
166 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register_unlocked()
173 static int send_command(struct mxl *state, u32 size, u8 *buf) in send_command() argument
178 mutex_lock(&state->base->i2c_lock); in send_command()
179 if (state->base->fwversion > 0x02010109) { in send_command()
180 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); in send_command()
182 dev_info(state->i2cdev, "%s busy\n", __func__); in send_command()
183 while ((DMA_INTR_PROT_WR_CMP & val) && --count) { in send_command()
184 mutex_unlock(&state->base->i2c_lock); in send_command()
186 mutex_lock(&state->base->i2c_lock); in send_command()
187 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, in send_command()
191 dev_info(state->i2cdev, "%s busy\n", __func__); in send_command()
192 mutex_unlock(&state->base->i2c_lock); in send_command()
193 return -EBUSY; in send_command()
196 stat = i2cwrite(state, buf, size); in send_command()
197 mutex_unlock(&state->base->i2c_lock); in send_command()
201 static int write_register(struct mxl *state, u32 reg, u32 val) in write_register() argument
209 mutex_lock(&state->base->i2c_lock); in write_register()
210 stat = i2cwrite(state, data, sizeof(data)); in write_register()
211 mutex_unlock(&state->base->i2c_lock); in write_register()
213 dev_err(state->i2cdev, "i2c write error\n"); in write_register()
217 static int write_firmware_block(struct mxl *state, in write_firmware_block() argument
221 u8 *buf = state->base->buf; in write_firmware_block()
223 mutex_lock(&state->base->i2c_lock); in write_firmware_block()
231 stat = i2cwrite(state, buf, in write_firmware_block()
234 mutex_unlock(&state->base->i2c_lock); in write_firmware_block()
236 dev_err(state->i2cdev, "fw block write failed\n"); in write_firmware_block()
240 static int read_register(struct mxl *state, u32 reg, u32 *val) in read_register() argument
249 mutex_lock(&state->base->i2c_lock); in read_register()
250 stat = i2cwrite(state, data, in read_register()
253 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register()
255 stat = i2cread(state, (u8 *) val, in read_register()
257 mutex_unlock(&state->base->i2c_lock); in read_register()
260 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register()
264 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) in read_register_block() argument
267 u8 *buf = state->base->buf; in read_register_block()
269 mutex_lock(&state->base->i2c_lock); in read_register_block()
277 stat = i2cwrite(state, buf, in read_register_block()
280 stat = i2cread(state, data, size); in read_register_block()
283 mutex_unlock(&state->base->i2c_lock); in read_register_block()
287 static int read_by_mnemonic(struct mxl *state, in read_by_mnemonic() argument
293 stat = read_register(state, reg, &data); in read_by_mnemonic()
304 static int update_by_mnemonic(struct mxl *state, in update_by_mnemonic() argument
310 stat = read_register(state, reg, &data); in update_by_mnemonic()
315 stat = write_register(state, reg, data); in update_by_mnemonic()
319 static int firmware_is_alive(struct mxl *state) in firmware_is_alive() argument
323 if (read_register(state, HYDRA_HEAR_BEAT, &hb0)) in firmware_is_alive()
326 if (read_register(state, HYDRA_HEAR_BEAT, &hb1)) in firmware_is_alive()
335 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in init()
338 p->strength.len = 1; in init()
339 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
340 p->cnr.len = 1; in init()
341 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
342 p->pre_bit_error.len = 1; in init()
343 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
344 p->pre_bit_count.len = 1; in init()
345 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
346 p->post_bit_error.len = 1; in init()
347 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
348 p->post_bit_count.len = 1; in init()
349 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in init()
356 struct mxl *state = fe->demodulator_priv; in release() local
358 list_del(&state->mxl); in release()
360 state->base->count--; in release()
361 if (state->base->count == 0) { in release()
362 list_del(&state->base->mxllist); in release()
363 kfree(state->base); in release()
365 kfree(state); in release()
384 static int cfg_scrambler(struct mxl *state, u32 gold) in cfg_scrambler() argument
390 state->demod, 0, 0, 0, in cfg_scrambler()
402 return send_command(state, sizeof(buf), buf); in cfg_scrambler()
405 static int cfg_demod_abort_tune(struct mxl *state) in cfg_demod_abort_tune() argument
411 abort_tune_cmd.demod_id = state->demod; in cfg_demod_abort_tune()
414 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in cfg_demod_abort_tune()
421 /*struct mxl *state = fe->demodulator_priv;*/ in send_master_cmd()
423 return 0; /*CfgDemodAbortTune(state);*/ in send_master_cmd()
428 struct mxl *state = fe->demodulator_priv; in set_parameters() local
429 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in set_parameters()
436 if (p->frequency < 950000 || p->frequency > 2150000) in set_parameters()
437 return -EINVAL; in set_parameters()
438 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000) in set_parameters()
439 return -EINVAL; in set_parameters()
441 /* CfgDemodAbortTune(state); */ in set_parameters()
443 switch (p->delivery_system) { in set_parameters()
449 srange = p->symbol_rate / 1000000; in set_parameters()
462 cfg_scrambler(state, p->scrambling_sequence_index); in set_parameters()
465 return -EINVAL; in set_parameters()
467 demod_chan_cfg.tuner_index = state->tuner; in set_parameters()
468 demod_chan_cfg.demod_index = state->demod; in set_parameters()
469 demod_chan_cfg.frequency_in_hz = p->frequency * 1000; in set_parameters()
470 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate; in set_parameters()
475 mutex_lock(&state->base->tune_lock); in set_parameters()
477 state->base->next_tune)) in set_parameters()
478 while (time_before(jiffies, state->base->next_tune)) in set_parameters()
480 state->base->next_tune = jiffies + msecs_to_jiffies(100); in set_parameters()
481 state->tuner_in_use = state->tuner; in set_parameters()
484 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in set_parameters()
486 mutex_unlock(&state->base->tune_lock); in set_parameters()
490 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
494 struct mxl *state = fe->demodulator_priv; in sleep() local
497 cfg_demod_abort_tune(state); in sleep()
498 if (state->tuner_in_use != 0xffffffff) { in sleep()
499 mutex_lock(&state->base->tune_lock); in sleep()
500 state->tuner_in_use = 0xffffffff; in sleep()
501 list_for_each_entry(p, &state->base->mxls, mxl) { in sleep()
502 if (p->tuner_in_use == state->tuner) in sleep()
505 if (&p->mxl == &state->base->mxls) in sleep()
506 enable_tuner(state, state->tuner, 0); in sleep()
507 mutex_unlock(&state->base->tune_lock); in sleep()
514 struct mxl *state = fe->demodulator_priv; in read_snr() local
517 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_snr()
519 mutex_lock(&state->base->status_lock); in read_snr()
520 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_snr()
521 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET + in read_snr()
522 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_snr()
524 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_snr()
525 mutex_unlock(&state->base->status_lock); in read_snr()
527 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in read_snr()
528 p->cnr.stat[0].svalue = (s16)reg_data * 10; in read_snr()
535 struct mxl *state = fe->demodulator_priv; in read_ber() local
536 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_ber()
539 mutex_lock(&state->base->status_lock); in read_ber()
540 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_ber()
541 read_register_block(state, in read_ber()
543 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_ber()
546 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_ber()
548 switch (p->delivery_system) { in read_ber()
551 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
552 p->pre_bit_error.stat[0].uvalue = reg[2]; in read_ber()
553 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
554 p->pre_bit_count.stat[0].uvalue = reg[3]; in read_ber()
560 read_register_block(state, in read_ber()
562 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_ber()
566 switch (p->delivery_system) { in read_ber()
569 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
570 p->post_bit_error.stat[0].uvalue = reg[5]; in read_ber()
571 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
572 p->post_bit_count.stat[0].uvalue = reg[6]; in read_ber()
575 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
576 p->post_bit_error.stat[0].uvalue = reg[1]; in read_ber()
577 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
578 p->post_bit_count.stat[0].uvalue = reg[2]; in read_ber()
584 mutex_unlock(&state->base->status_lock); in read_ber()
591 struct mxl *state = fe->demodulator_priv; in read_signal_strength() local
592 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_signal_strength()
596 mutex_lock(&state->base->status_lock); in read_signal_strength()
597 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_signal_strength()
598 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR + in read_signal_strength()
599 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_signal_strength()
601 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_signal_strength()
602 mutex_unlock(&state->base->status_lock); in read_signal_strength()
604 p->strength.stat[0].scale = FE_SCALE_DECIBEL; in read_signal_strength()
605 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */ in read_signal_strength()
612 struct mxl *state = fe->demodulator_priv; in read_status() local
613 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in read_status()
616 mutex_lock(&state->base->status_lock); in read_status()
617 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_status()
618 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET + in read_status()
619 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_status()
621 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_status()
622 mutex_unlock(&state->base->status_lock); in read_status()
634 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
639 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
640 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
641 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
642 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
652 struct mxl *state = fe->demodulator_priv; in tune() local
660 state->tune_time = jiffies; in tune()
682 struct mxl *state = fe->demodulator_priv; in get_frontend() local
686 mutex_lock(&state->base->status_lock); in get_frontend()
687 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in get_frontend()
688 read_register_block(state, in get_frontend()
690 HYDRA_DMD_STATUS_OFFSET(state->demod)), in get_frontend()
694 read_register_block(state, in get_frontend()
696 HYDRA_DMD_STATUS_OFFSET(state->demod)), in get_frontend()
699 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in get_frontend()
700 mutex_unlock(&state->base->status_lock); in get_frontend()
702 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n", in get_frontend()
705 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR]; in get_frontend()
706 p->frequency = freq; in get_frontend()
708 * p->delivery_system = in get_frontend()
710 * p->inversion = in get_frontend()
716 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]); in get_frontend()
717 switch (p->delivery_system) { in get_frontend()
724 p->pilot = PILOT_OFF; in get_frontend()
727 p->pilot = PILOT_ON; in get_frontend()
737 p->modulation = QPSK; in get_frontend()
740 p->modulation = PSK_8; in get_frontend()
748 p->rolloff = ROLLOFF_20; in get_frontend()
751 p->rolloff = ROLLOFF_35; in get_frontend()
754 p->rolloff = ROLLOFF_25; in get_frontend()
761 return -EINVAL; in get_frontend()
768 struct mxl *state = fe->demodulator_priv; in set_input() local
770 state->tuner = input; in set_input()
777 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
802 if (p->i2c == i2c && p->adr == adr) in match_base()
807 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable) in cfg_dev_xtal() argument
809 if (state->base->can_clkout || !enable) in cfg_dev_xtal()
810 update_by_mnemonic(state, 0x90200054, 23, 1, enable); in cfg_dev_xtal()
813 write_register(state, HYDRA_CRYSTAL_SETTING, 0); in cfg_dev_xtal()
815 write_register(state, HYDRA_CRYSTAL_SETTING, 1); in cfg_dev_xtal()
817 write_register(state, HYDRA_CRYSTAL_CAP, cap); in cfg_dev_xtal()
841 static int write_fw_segment(struct mxl *state, in write_fw_segment() argument
849 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - in write_fw_segment()
852 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - in write_fw_segment()
857 (total_size - data_count) : block_size; in write_fw_segment()
865 status = write_firmware_block(state, mem_addr, size, w_buf_ptr); in write_fw_segment()
876 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr, in do_firmware_download() argument
888 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) { in do_firmware_download()
889 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n", in do_firmware_download()
890 __func__, mbin_ptr->header.id); in do_firmware_download()
891 return -EINVAL; in do_firmware_download()
893 status = write_register(state, FW_DL_SIGN_ADDR, 0); in do_firmware_download()
896 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]); in do_firmware_download()
897 for (index = 0; index < mbin_ptr->header.num_segments; index++) { in do_firmware_download()
898 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) { in do_firmware_download()
899 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n", in do_firmware_download()
900 __func__, segment_ptr->header.id); in do_firmware_download()
901 return -EINVAL; in do_firmware_download()
904 &(segment_ptr->header.len24[0])); in do_firmware_download()
906 &(segment_ptr->header.address[0])); in do_firmware_download()
908 if (state->base->type == MXL_HYDRA_DEVICE_568) { in do_firmware_download()
912 update_by_mnemonic(state, 0x8003003C, 0, 1, 1); in do_firmware_download()
914 write_register(state, 0x90720000, 0); in do_firmware_download()
918 status = write_fw_segment(state, seg_address, in do_firmware_download()
920 (u8 *) segment_ptr->data); in do_firmware_download()
924 status = write_fw_segment(state, seg_address, in do_firmware_download()
925 seg_length, (u8 *) segment_ptr->data); in do_firmware_download()
930 &(segment_ptr->data[((seg_length + 3) / 4) * 4]); in do_firmware_download()
935 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len) in check_fw() argument
938 u32 flen = (fh->image_size24[0] << 16) | in check_fw()
939 (fh->image_size24[1] << 8) | fh->image_size24[2]; in check_fw()
943 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) { in check_fw()
944 dev_info(state->i2cdev, "Invalid FW Header\n"); in check_fw()
945 return -1; in check_fw()
950 if (cs != fh->image_checksum) { in check_fw()
951 dev_info(state->i2cdev, "Invalid FW Checksum\n"); in check_fw()
952 return -1; in check_fw()
957 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) in firmware_download() argument
965 if (check_fw(state, mbin, mbin_len)) in firmware_download()
966 return -1; in firmware_download()
969 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0); in firmware_download()
975 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG, in firmware_download()
979 status = write_register(state, HYDRA_RESET_BBAND_REG, in firmware_download()
983 status = write_register(state, HYDRA_RESET_XBAR_REG, in firmware_download()
991 status = write_register(state, HYDRA_MODULES_CLK_2_REG, in firmware_download()
995 /* Clear Software & Host interrupt status - (Clear on read) */ in firmware_download()
996 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data); in firmware_download()
999 status = do_firmware_download(state, mbin, mbin_len); in firmware_download()
1003 if (state->base->type == MXL_HYDRA_DEVICE_568) { in firmware_download()
1007 status = write_register(state, 0x90720000, 1); in firmware_download()
1013 status = write_register(state, 0x9076B510, 1); in firmware_download()
1018 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1); in firmware_download()
1026 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210); in firmware_download()
1030 if (!firmware_is_alive(state)) in firmware_download()
1031 return -1; in firmware_download()
1033 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n"); in firmware_download()
1040 dev_sku_cfg.sku_type = state->base->sku_type; in firmware_download()
1043 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in firmware_download()
1049 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts) in cfg_ts_pad_mux() argument
1056 if ((state->base->type == MXL_HYDRA_DEVICE_541) || in cfg_ts_pad_mux()
1057 (state->base->type == MXL_HYDRA_DEVICE_541S)) in cfg_ts_pad_mux()
1060 if ((state->base->type == MXL_HYDRA_DEVICE_581) || in cfg_ts_pad_mux()
1061 (state->base->type == MXL_HYDRA_DEVICE_581S)) in cfg_ts_pad_mux()
1067 switch (state->base->type) { in cfg_ts_pad_mux()
1074 status |= update_by_mnemonic(state, 0x90000170, 24, 3, in cfg_ts_pad_mux()
1076 status |= update_by_mnemonic(state, 0x90000170, 28, 3, in cfg_ts_pad_mux()
1078 status |= update_by_mnemonic(state, 0x90000174, 0, 3, in cfg_ts_pad_mux()
1080 status |= update_by_mnemonic(state, 0x90000174, 4, 3, in cfg_ts_pad_mux()
1082 status |= update_by_mnemonic(state, 0x90000174, 8, 3, in cfg_ts_pad_mux()
1084 status |= update_by_mnemonic(state, 0x90000174, 12, 3, in cfg_ts_pad_mux()
1086 status |= update_by_mnemonic(state, 0x90000174, 16, 3, in cfg_ts_pad_mux()
1088 status |= update_by_mnemonic(state, 0x90000174, 20, 3, in cfg_ts_pad_mux()
1090 status |= update_by_mnemonic(state, 0x90000174, 24, 3, in cfg_ts_pad_mux()
1092 status |= update_by_mnemonic(state, 0x90000174, 28, 3, in cfg_ts_pad_mux()
1094 status |= update_by_mnemonic(state, 0x90000178, 0, 3, in cfg_ts_pad_mux()
1096 status |= update_by_mnemonic(state, 0x90000178, 4, 3, in cfg_ts_pad_mux()
1098 status |= update_by_mnemonic(state, 0x90000178, 8, 3, in cfg_ts_pad_mux()
1104 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1); in cfg_ts_pad_mux()
1105 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0); in cfg_ts_pad_mux()
1106 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0); in cfg_ts_pad_mux()
1107 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0); in cfg_ts_pad_mux()
1108 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0); in cfg_ts_pad_mux()
1109 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1); in cfg_ts_pad_mux()
1110 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1); in cfg_ts_pad_mux()
1111 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1); in cfg_ts_pad_mux()
1112 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1); in cfg_ts_pad_mux()
1113 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1); in cfg_ts_pad_mux()
1114 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1); in cfg_ts_pad_mux()
1116 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1118 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1120 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1122 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1124 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1126 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1128 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1130 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1132 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1134 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1136 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1138 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1140 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1142 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1144 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1146 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1148 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1150 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1153 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1155 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1157 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1159 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1161 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1163 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1165 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1167 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1169 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1171 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1173 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1175 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1177 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1179 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1181 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1183 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1185 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1187 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1194 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1196 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1198 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1200 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1202 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1204 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1206 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1208 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1210 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1212 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1214 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1216 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1219 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1221 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1223 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1225 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1227 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1229 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1231 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1233 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1235 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1237 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1239 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1242 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1244 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1246 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1248 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1250 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1252 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1254 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1256 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1259 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1261 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1263 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1265 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1267 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1269 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1271 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1273 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1275 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1277 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1279 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1287 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1289 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1291 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1293 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1295 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1297 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1299 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1301 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1303 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1305 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1307 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1314 static int set_drive_strength(struct mxl *state, in set_drive_strength() argument
1320 read_register(state, 0x90000194, &val); in set_drive_strength()
1321 dev_info(state->i2cdev, "DIGIO = %08x\n", val); in set_drive_strength()
1322 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength); in set_drive_strength()
1325 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength); in set_drive_strength()
1326 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength); in set_drive_strength()
1327 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength); in set_drive_strength()
1328 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength); in set_drive_strength()
1329 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength); in set_drive_strength()
1330 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength); in set_drive_strength()
1331 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength); in set_drive_strength()
1332 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength); in set_drive_strength()
1333 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength); in set_drive_strength()
1334 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength); in set_drive_strength()
1335 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength); in set_drive_strength()
1336 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength); in set_drive_strength()
1337 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength); in set_drive_strength()
1338 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength); in set_drive_strength()
1339 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength); in set_drive_strength()
1340 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength); in set_drive_strength()
1341 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength); in set_drive_strength()
1346 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable) in enable_tuner() argument
1358 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in enable_tuner()
1362 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); in enable_tuner()
1363 while (--count && ((val >> tuner) & 1) != enable) { in enable_tuner()
1365 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); in enable_tuner()
1368 return -1; in enable_tuner()
1369 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); in enable_tuner()
1370 dev_dbg(state->i2cdev, "tuner %u ready = %u\n", in enable_tuner()
1377 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id, in config_ts() argument
1440 demod_id = state->base->ts_map[demod_id]; in config_ts()
1442 if (mpeg_out_param_ptr->enable == MXL_ENABLE) { in config_ts()
1443 if (mpeg_out_param_ptr->mpeg_mode == in config_ts()
1446 cfg_ts_pad_mux(state, MXL_TRUE); in config_ts()
1447 update_by_mnemonic(state, in config_ts()
1453 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate); in config_ts()
1455 if (state->base->chipversion >= 2) { in config_ts()
1456 status |= update_by_mnemonic(state, in config_ts()
1462 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min); in config_ts()
1464 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS) in config_ts()
1467 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) { in config_ts()
1468 status |= update_by_mnemonic(state, in config_ts()
1474 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); in config_ts()
1476 status |= update_by_mnemonic(state, in config_ts()
1480 mpeg_out_param_ptr->mpeg_sync_pol); in config_ts()
1482 status |= update_by_mnemonic(state, in config_ts()
1486 mpeg_out_param_ptr->mpeg_valid_pol); in config_ts()
1488 status |= update_by_mnemonic(state, in config_ts()
1492 mpeg_out_param_ptr->mpeg_clk_pol); in config_ts()
1494 status |= update_by_mnemonic(state, in config_ts()
1498 mpeg_out_param_ptr->mpeg_sync_pulse_width); in config_ts()
1500 status |= update_by_mnemonic(state, in config_ts()
1504 mpeg_out_param_ptr->mpeg_clk_phase); in config_ts()
1506 status |= update_by_mnemonic(state, in config_ts()
1510 mpeg_out_param_ptr->lsb_or_msb_first); in config_ts()
1512 switch (mpeg_out_param_ptr->mpeg_error_indication) { in config_ts()
1514 status |= update_by_mnemonic(state, in config_ts()
1519 status |= update_by_mnemonic(state, in config_ts()
1527 status |= update_by_mnemonic(state, in config_ts()
1533 status |= update_by_mnemonic(state, in config_ts()
1542 status |= update_by_mnemonic(state, in config_ts()
1548 status |= update_by_mnemonic(state, in config_ts()
1558 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) { in config_ts()
1559 status |= update_by_mnemonic(state, in config_ts()
1563 mpeg_out_param_ptr->enable); in config_ts()
1568 static int config_mux(struct mxl *state) in config_mux() argument
1570 update_by_mnemonic(state, 0x9070000C, 0, 1, 0); in config_mux()
1571 update_by_mnemonic(state, 0x9070000C, 1, 1, 0); in config_mux()
1572 update_by_mnemonic(state, 0x9070000C, 2, 1, 0); in config_mux()
1573 update_by_mnemonic(state, 0x9070000C, 3, 1, 0); in config_mux()
1574 update_by_mnemonic(state, 0x9070000C, 4, 1, 0); in config_mux()
1575 update_by_mnemonic(state, 0x9070000C, 5, 1, 0); in config_mux()
1576 update_by_mnemonic(state, 0x9070000C, 6, 1, 0); in config_mux()
1577 update_by_mnemonic(state, 0x9070000C, 7, 1, 0); in config_mux()
1578 update_by_mnemonic(state, 0x90700008, 0, 2, 1); in config_mux()
1579 update_by_mnemonic(state, 0x90700008, 2, 2, 1); in config_mux()
1583 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) in load_fw() argument
1588 if (cfg->fw) in load_fw()
1589 return firmware_download(state, cfg->fw, cfg->fw_len); in load_fw()
1591 if (!cfg->fw_read) in load_fw()
1592 return -1; in load_fw()
1596 return -ENOMEM; in load_fw()
1598 cfg->fw_read(cfg->fw_priv, buf, 0x40000); in load_fw()
1599 stat = firmware_download(state, buf, 0x40000); in load_fw()
1605 static int validate_sku(struct mxl *state) in validate_sku() argument
1609 u32 type = state->base->type; in validate_sku()
1611 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond); in validate_sku()
1612 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id); in validate_sku()
1613 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid); in validate_sku()
1615 return -1; in validate_sku()
1617 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n", in validate_sku()
1626 state->base->type = MXL_HYDRA_DEVICE_581; in validate_sku()
1645 return -1; in validate_sku()
1650 return -1; in validate_sku()
1653 static int get_fwinfo(struct mxl *state) in get_fwinfo() argument
1658 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val); in get_fwinfo()
1661 dev_info(state->i2cdev, "chipID=%08x\n", val); in get_fwinfo()
1663 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val); in get_fwinfo()
1666 dev_info(state->i2cdev, "chipVer=%08x\n", val); in get_fwinfo()
1668 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val); in get_fwinfo()
1671 dev_info(state->i2cdev, "FWVer=%08x\n", val); in get_fwinfo()
1673 state->base->fwversion = val; in get_fwinfo()
1700 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg) in probe() argument
1706 state->base->ts_map = ts_map1_to_1; in probe()
1708 switch (state->base->type) { in probe()
1711 state->base->can_clkout = 1; in probe()
1712 state->base->demod_num = 8; in probe()
1713 state->base->tuner_num = 1; in probe()
1714 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; in probe()
1717 state->base->can_clkout = 1; in probe()
1718 state->base->demod_num = 8; in probe()
1719 state->base->tuner_num = 3; in probe()
1720 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; in probe()
1723 state->base->can_clkout = 0; in probe()
1724 state->base->demod_num = 8; in probe()
1725 state->base->tuner_num = 4; in probe()
1726 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; in probe()
1729 state->base->can_clkout = 0; in probe()
1730 state->base->demod_num = 4; in probe()
1731 state->base->tuner_num = 4; in probe()
1732 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; in probe()
1733 state->base->ts_map = ts_map54x; in probe()
1737 state->base->can_clkout = 0; in probe()
1738 state->base->demod_num = 4; in probe()
1739 state->base->tuner_num = 1; in probe()
1740 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; in probe()
1741 state->base->ts_map = ts_map54x; in probe()
1745 state->base->can_clkout = 0; in probe()
1746 state->base->demod_num = 6; in probe()
1747 state->base->tuner_num = 1; in probe()
1748 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; in probe()
1751 state->base->can_clkout = 0; in probe()
1752 state->base->demod_num = 8; in probe()
1753 state->base->tuner_num = 1; in probe()
1754 state->base->chan_bond = 1; in probe()
1755 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; in probe()
1758 state->base->can_clkout = 1; in probe()
1759 state->base->demod_num = 4; in probe()
1760 state->base->tuner_num = 3; in probe()
1761 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; in probe()
1762 state->base->ts_map = ts_map54x; in probe()
1767 state->base->can_clkout = 0; in probe()
1768 state->base->demod_num = 8; in probe()
1769 state->base->tuner_num = 4; in probe()
1770 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; in probe()
1774 status = validate_sku(state); in probe()
1778 update_by_mnemonic(state, 0x80030014, 9, 1, 1); in probe()
1779 update_by_mnemonic(state, 0x8003003C, 12, 1, 1); in probe()
1780 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver); in probe()
1782 state->base->chipversion = 0; in probe()
1784 state->base->chipversion = (chipver == 2) ? 2 : 1; in probe()
1785 dev_info(state->i2cdev, "Hydra chip version %u\n", in probe()
1786 state->base->chipversion); in probe()
1788 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0); in probe()
1790 fw = firmware_is_alive(state); in probe()
1792 status = load_fw(state, cfg); in probe()
1796 get_fwinfo(state); in probe()
1798 config_mux(state); in probe()
1801 /* supports only (0-104&139)MHz */ in probe()
1802 if (cfg->ts_clk) in probe()
1803 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk; in probe()
1817 for (j = 0; j < state->base->demod_num; j++) { in probe()
1818 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j, in probe()
1823 set_drive_strength(state, 1); in probe()
1831 struct mxl *state; in mxl5xx_attach() local
1834 state = kzalloc(sizeof(struct mxl), GFP_KERNEL); in mxl5xx_attach()
1835 if (!state) in mxl5xx_attach()
1838 state->demod = demod; in mxl5xx_attach()
1839 state->tuner = tuner; in mxl5xx_attach()
1840 state->tuner_in_use = 0xffffffff; in mxl5xx_attach()
1841 state->i2cdev = &i2c->dev; in mxl5xx_attach()
1843 base = match_base(i2c, cfg->adr); in mxl5xx_attach()
1845 base->count++; in mxl5xx_attach()
1846 if (base->count > base->demod_num) in mxl5xx_attach()
1848 state->base = base; in mxl5xx_attach()
1853 base->i2c = i2c; in mxl5xx_attach()
1854 base->adr = cfg->adr; in mxl5xx_attach()
1855 base->type = cfg->type; in mxl5xx_attach()
1856 base->count = 1; in mxl5xx_attach()
1857 mutex_init(&base->i2c_lock); in mxl5xx_attach()
1858 mutex_init(&base->status_lock); in mxl5xx_attach()
1859 mutex_init(&base->tune_lock); in mxl5xx_attach()
1860 INIT_LIST_HEAD(&base->mxls); in mxl5xx_attach()
1862 state->base = base; in mxl5xx_attach()
1863 if (probe(state, cfg) < 0) { in mxl5xx_attach()
1867 list_add(&base->mxllist, &mxllist); in mxl5xx_attach()
1869 state->fe.ops = mxl_ops; in mxl5xx_attach()
1870 state->xbar[0] = 4; in mxl5xx_attach()
1871 state->xbar[1] = demod; in mxl5xx_attach()
1872 state->xbar[2] = 8; in mxl5xx_attach()
1873 state->fe.demodulator_priv = state; in mxl5xx_attach()
1876 list_add(&state->mxl, &base->mxls); in mxl5xx_attach()
1877 return &state->fe; in mxl5xx_attach()
1880 kfree(state); in mxl5xx_attach()
1885 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");