Lines Matching +full:scl +full:- +full:open +full:- +full:drain
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxk_hard: DRX-K DVB-C/T demodulator driver
5 * Copyright (C) 2010-2011 Digital Devices GmbH
45 return state->m_operation_mode == OM_DVBT; in is_dvbt()
50 return state->m_operation_mode == OM_QAM_ITU_A || in is_qam()
51 state->m_operation_mode == OM_QAM_ITU_B || in is_qam()
52 state->m_operation_mode == OM_QAM_ITU_C; in is_qam()
164 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ in Frac28a()
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_lock()
194 state->drxk_i2c_exclusive_lock = true; in drxk_i2c_lock()
201 if (!state->drxk_i2c_exclusive_lock) in drxk_i2c_unlock()
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_unlock()
205 state->drxk_i2c_exclusive_lock = false; in drxk_i2c_unlock()
211 if (state->drxk_i2c_exclusive_lock) in drxk_i2c_transfer()
212 return __i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
214 return i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
241 status = -EIO; in i2c_write()
265 status = -EIO; in i2c_read()
286 u8 adr = state->demod_address, mm1[4], mm2[2], len; in read16_flags()
288 if (state->single_master) in read16_flags()
320 u8 adr = state->demod_address, mm1[4], mm2[4], len; in read32_flags()
322 if (state->single_master) in read32_flags()
354 u8 adr = state->demod_address, mm[6], len; in write16_flags()
356 if (state->single_master) in write16_flags()
383 u8 adr = state->demod_address, mm[8], len; in write32_flags()
385 if (state->single_master) in write32_flags()
418 if (state->single_master) in write_block()
422 int chunk = blk_size > state->m_chunk_size ? in write_block()
423 state->m_chunk_size : blk_size; in write_block()
424 u8 *adr_buf = &state->chunk[0]; in write_block()
434 if (chunk == state->m_chunk_size) in write_block()
435 chunk -= 2; in write_block()
442 memcpy(&state->chunk[adr_length], p_block, chunk); in write_block()
451 status = i2c_write(state, state->demod_address, in write_block()
452 &state->chunk[0], chunk + adr_length); in write_block()
460 blk_size -= chunk; in write_block()
477 status = i2c_read1(state, state->demod_address, &data); in power_up_device()
481 status = i2c_write(state, state->demod_address, in power_up_device()
487 status = i2c_read1(state, state->demod_address, in power_up_device()
507 state->m_current_power_mode = DRX_POWER_UP; in power_up_device()
521 * struct drxk_config, as they are probably board-specific in init_state()
573 state->m_has_lna = false; in init_state()
574 state->m_has_dvbt = false; in init_state()
575 state->m_has_dvbc = false; in init_state()
576 state->m_has_atv = false; in init_state()
577 state->m_has_oob = false; in init_state()
578 state->m_has_audio = false; in init_state()
580 if (!state->m_chunk_size) in init_state()
581 state->m_chunk_size = 124; in init_state()
583 state->m_osc_clock_freq = 0; in init_state()
584 state->m_smart_ant_inverted = false; in init_state()
585 state->m_b_p_down_open_bridge = false; in init_state()
588 state->m_sys_clock_freq = 151875; in init_state()
591 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * in init_state()
594 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_state()
595 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_state()
596 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_state()
598 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_state()
600 state->m_b_power_down = (ul_power_down != 0); in init_state()
602 state->m_drxk_a3_patch_code = false; in init_state()
606 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; in init_state()
607 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; in init_state()
608 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; in init_state()
609 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; in init_state()
610 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; in init_state()
611 state->m_vsb_pga_cfg = 140; in init_state()
614 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; in init_state()
615 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; in init_state()
616 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; in init_state()
617 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; in init_state()
618 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; in init_state()
619 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; in init_state()
620 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; in init_state()
621 state->m_vsb_pre_saw_cfg.reference = 0x07; in init_state()
622 state->m_vsb_pre_saw_cfg.use_pre_saw = true; in init_state()
624 state->m_Quality83percent = DEFAULT_MER_83; in init_state()
625 state->m_Quality93percent = DEFAULT_MER_93; in init_state()
627 state->m_Quality83percent = ulQual83; in init_state()
628 state->m_Quality93percent = ulQual93; in init_state()
632 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; in init_state()
633 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; in init_state()
634 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; in init_state()
635 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; in init_state()
636 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; in init_state()
639 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; in init_state()
640 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; in init_state()
641 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; in init_state()
642 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; in init_state()
643 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; in init_state()
644 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; in init_state()
645 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; in init_state()
646 state->m_atv_pre_saw_cfg.reference = 0x04; in init_state()
647 state->m_atv_pre_saw_cfg.use_pre_saw = true; in init_state()
651 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
652 state->m_dvbt_rf_agc_cfg.output_level = 0; in init_state()
653 state->m_dvbt_rf_agc_cfg.min_output_level = 0; in init_state()
654 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; in init_state()
655 state->m_dvbt_rf_agc_cfg.top = 0x2100; in init_state()
656 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; in init_state()
657 state->m_dvbt_rf_agc_cfg.speed = 1; in init_state()
661 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
662 state->m_dvbt_if_agc_cfg.output_level = 0; in init_state()
663 state->m_dvbt_if_agc_cfg.min_output_level = 0; in init_state()
664 state->m_dvbt_if_agc_cfg.max_output_level = 9000; in init_state()
665 state->m_dvbt_if_agc_cfg.top = 13424; in init_state()
666 state->m_dvbt_if_agc_cfg.cut_off_current = 0; in init_state()
667 state->m_dvbt_if_agc_cfg.speed = 3; in init_state()
668 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; in init_state()
669 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; in init_state()
670 /* state->m_dvbtPgaCfg = 140; */ in init_state()
672 state->m_dvbt_pre_saw_cfg.reference = 4; in init_state()
673 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; in init_state()
676 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
677 state->m_qam_rf_agc_cfg.output_level = 0; in init_state()
678 state->m_qam_rf_agc_cfg.min_output_level = 6023; in init_state()
679 state->m_qam_rf_agc_cfg.max_output_level = 27000; in init_state()
680 state->m_qam_rf_agc_cfg.top = 0x2380; in init_state()
681 state->m_qam_rf_agc_cfg.cut_off_current = 4000; in init_state()
682 state->m_qam_rf_agc_cfg.speed = 3; in init_state()
685 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
686 state->m_qam_if_agc_cfg.output_level = 0; in init_state()
687 state->m_qam_if_agc_cfg.min_output_level = 0; in init_state()
688 state->m_qam_if_agc_cfg.max_output_level = 9000; in init_state()
689 state->m_qam_if_agc_cfg.top = 0x0511; in init_state()
690 state->m_qam_if_agc_cfg.cut_off_current = 0; in init_state()
691 state->m_qam_if_agc_cfg.speed = 3; in init_state()
692 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; in init_state()
693 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; in init_state()
695 state->m_qam_pga_cfg = 140; in init_state()
696 state->m_qam_pre_saw_cfg.reference = 4; in init_state()
697 state->m_qam_pre_saw_cfg.use_pre_saw = false; in init_state()
699 state->m_operation_mode = OM_NONE; in init_state()
700 state->m_drxk_state = DRXK_UNINITIALIZED; in init_state()
703 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */ in init_state()
704 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ in init_state()
705 state->m_invert_data = false; /* If TRUE; invert DATA signals */ in init_state()
706 state->m_invert_err = false; /* If TRUE; invert ERR signal */ in init_state()
707 state->m_invert_str = false; /* If TRUE; invert STR signals */ in init_state()
708 state->m_invert_val = false; /* If TRUE; invert VAL signals */ in init_state()
709 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ in init_state()
714 state->m_dvbt_bitrate = ul_dvbt_bitrate; in init_state()
715 state->m_dvbc_bitrate = ul_dvbc_bitrate; in init_state()
717 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); in init_state()
720 state->m_mpeg_ts_static_bitrate = 19392658; in init_state()
721 state->m_disable_te_ihandling = false; in init_state()
724 state->m_insert_rs_byte = true; in init_state()
726 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; in init_state()
728 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; in init_state()
729 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; in init_state()
731 state->m_demod_lock_time_out = ul_demod_lock_time_out; in init_state()
734 state->m_constellation = DRX_CONSTELLATION_AUTO; in init_state()
735 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; in init_state()
736 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ in init_state()
737 state->m_fec_rs_prescale = 1; in init_state()
739 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; in init_state()
740 state->m_agcfast_clip_ctrl_delay = 0; in init_state()
742 state->m_gpio_cfg = ul_gpio_cfg; in init_state()
744 state->m_b_power_down = false; in init_state()
745 state->m_current_power_mode = DRX_POWER_DOWN; in init_state()
747 state->m_rfmirror = (ul_rf_mirror == 0); in init_state()
748 state->m_if_agc_pol = false; in init_state()
816 state->m_osc_clock_freq = 27000; in get_device_capabilities()
820 state->m_osc_clock_freq = 20250; in get_device_capabilities()
824 state->m_osc_clock_freq = 20250; in get_device_capabilities()
828 return -EINVAL; in get_device_capabilities()
843 state->m_device_spin = DRXK_SPIN_A1; in get_device_capabilities()
847 state->m_device_spin = DRXK_SPIN_A2; in get_device_capabilities()
851 state->m_device_spin = DRXK_SPIN_A3; in get_device_capabilities()
855 state->m_device_spin = DRXK_SPIN_UNKNOWN; in get_device_capabilities()
856 status = -EINVAL; in get_device_capabilities()
863 state->m_has_lna = false; in get_device_capabilities()
864 state->m_has_oob = false; in get_device_capabilities()
865 state->m_has_atv = false; in get_device_capabilities()
866 state->m_has_audio = false; in get_device_capabilities()
867 state->m_has_dvbt = true; in get_device_capabilities()
868 state->m_has_dvbc = true; in get_device_capabilities()
869 state->m_has_sawsw = true; in get_device_capabilities()
870 state->m_has_gpio2 = false; in get_device_capabilities()
871 state->m_has_gpio1 = false; in get_device_capabilities()
872 state->m_has_irqn = false; in get_device_capabilities()
876 state->m_has_lna = false; in get_device_capabilities()
877 state->m_has_oob = false; in get_device_capabilities()
878 state->m_has_atv = true; in get_device_capabilities()
879 state->m_has_audio = false; in get_device_capabilities()
880 state->m_has_dvbt = true; in get_device_capabilities()
881 state->m_has_dvbc = false; in get_device_capabilities()
882 state->m_has_sawsw = true; in get_device_capabilities()
883 state->m_has_gpio2 = true; in get_device_capabilities()
884 state->m_has_gpio1 = true; in get_device_capabilities()
885 state->m_has_irqn = false; in get_device_capabilities()
889 state->m_has_lna = false; in get_device_capabilities()
890 state->m_has_oob = false; in get_device_capabilities()
891 state->m_has_atv = true; in get_device_capabilities()
892 state->m_has_audio = false; in get_device_capabilities()
893 state->m_has_dvbt = true; in get_device_capabilities()
894 state->m_has_dvbc = false; in get_device_capabilities()
895 state->m_has_sawsw = true; in get_device_capabilities()
896 state->m_has_gpio2 = true; in get_device_capabilities()
897 state->m_has_gpio1 = true; in get_device_capabilities()
898 state->m_has_irqn = false; in get_device_capabilities()
902 state->m_has_lna = false; in get_device_capabilities()
903 state->m_has_oob = false; in get_device_capabilities()
904 state->m_has_atv = true; in get_device_capabilities()
905 state->m_has_audio = true; in get_device_capabilities()
906 state->m_has_dvbt = true; in get_device_capabilities()
907 state->m_has_dvbc = false; in get_device_capabilities()
908 state->m_has_sawsw = true; in get_device_capabilities()
909 state->m_has_gpio2 = true; in get_device_capabilities()
910 state->m_has_gpio1 = true; in get_device_capabilities()
911 state->m_has_irqn = false; in get_device_capabilities()
915 state->m_has_lna = false; in get_device_capabilities()
916 state->m_has_oob = false; in get_device_capabilities()
917 state->m_has_atv = true; in get_device_capabilities()
918 state->m_has_audio = true; in get_device_capabilities()
919 state->m_has_dvbt = true; in get_device_capabilities()
920 state->m_has_dvbc = true; in get_device_capabilities()
921 state->m_has_sawsw = true; in get_device_capabilities()
922 state->m_has_gpio2 = true; in get_device_capabilities()
923 state->m_has_gpio1 = true; in get_device_capabilities()
924 state->m_has_irqn = false; in get_device_capabilities()
928 state->m_has_lna = false; in get_device_capabilities()
929 state->m_has_oob = false; in get_device_capabilities()
930 state->m_has_atv = true; in get_device_capabilities()
931 state->m_has_audio = true; in get_device_capabilities()
932 state->m_has_dvbt = true; in get_device_capabilities()
933 state->m_has_dvbc = true; in get_device_capabilities()
934 state->m_has_sawsw = true; in get_device_capabilities()
935 state->m_has_gpio2 = true; in get_device_capabilities()
936 state->m_has_gpio1 = true; in get_device_capabilities()
937 state->m_has_irqn = false; in get_device_capabilities()
941 state->m_has_lna = false; in get_device_capabilities()
942 state->m_has_oob = false; in get_device_capabilities()
943 state->m_has_atv = true; in get_device_capabilities()
944 state->m_has_audio = true; in get_device_capabilities()
945 state->m_has_dvbt = true; in get_device_capabilities()
946 state->m_has_dvbc = true; in get_device_capabilities()
947 state->m_has_sawsw = true; in get_device_capabilities()
948 state->m_has_gpio2 = true; in get_device_capabilities()
949 state->m_has_gpio1 = true; in get_device_capabilities()
950 state->m_has_irqn = false; in get_device_capabilities()
954 state->m_has_lna = false; in get_device_capabilities()
955 state->m_has_oob = false; in get_device_capabilities()
956 state->m_has_atv = true; in get_device_capabilities()
957 state->m_has_audio = false; in get_device_capabilities()
958 state->m_has_dvbt = true; in get_device_capabilities()
959 state->m_has_dvbc = true; in get_device_capabilities()
960 state->m_has_sawsw = true; in get_device_capabilities()
961 state->m_has_gpio2 = true; in get_device_capabilities()
962 state->m_has_gpio1 = true; in get_device_capabilities()
963 state->m_has_irqn = false; in get_device_capabilities()
968 status = -EINVAL; in get_device_capabilities()
972 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", in get_device_capabilities()
974 state->m_osc_clock_freq / 1000, in get_device_capabilities()
975 state->m_osc_clock_freq % 1000); in get_device_capabilities()
1001 ((state->m_hi_cfg_ctrl) & in hi_command()
1032 mutex_lock(&state->mutex); in hi_cfg_command()
1035 state->m_hi_cfg_timeout); in hi_cfg_command()
1039 state->m_hi_cfg_ctrl); in hi_cfg_command()
1043 state->m_hi_cfg_wake_up_key); in hi_cfg_command()
1047 state->m_hi_cfg_bridge_delay); in hi_cfg_command()
1051 state->m_hi_cfg_timing_div); in hi_cfg_command()
1062 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in hi_cfg_command()
1064 mutex_unlock(&state->mutex); in hi_cfg_command()
1074 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_hi()
1075 state->m_hi_cfg_timeout = 0x96FF; in init_hi()
1077 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_hi()
1091 state->m_enable_parallel ? "parallel" : "serial"); in mpegts_configure_pins()
1145 ((state->m_ts_data_strength << in mpegts_configure_pins()
1147 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << in mpegts_configure_pins()
1155 if (state->enable_merr_cfg) in mpegts_configure_pins()
1165 if (state->m_enable_parallel) { in mpegts_configure_pins()
1166 /* parallel -> enable MD1 to MD7 */ in mpegts_configure_pins()
1196 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << in mpegts_configure_pins()
1199 /* serial -> disable MD1 to MD7 */ in mpegts_configure_pins()
1256 mutex_lock(&state->mutex); in bl_chain_cmd()
1281 status = -EINVAL; in bl_chain_cmd()
1288 mutex_unlock(&state->mutex); in bl_chain_cmd()
1306 /* down the drain (we don't care about MAGIC_WORD) */ in download_microcode()
1309 drain = (p_src[0] << 8) | p_src[1]; in download_microcode()
1343 return -EINVAL; in download_microcode()
1390 return -EINVAL; in dvbt_enable_ofdm_token_ring()
1430 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 in scu_command()
1434 int status = -EINVAL; in scu_command()
1449 mutex_lock(&state->mutex); in scu_command()
1454 for (ii = parameter_len - 1; ii >= 0; ii -= 1) { in scu_command()
1462 write_block(state, SCU_RAM_PARAM_0__A - in scu_command()
1463 (parameter_len - 1), cnt, buffer); in scu_command()
1474 status = -EIO; in scu_command()
1482 for (ii = result_len - 1; ii >= 0; ii -= 1) { in scu_command()
1483 status = read16(state, SCU_RAM_PARAM_0__A - ii, in scu_command()
1514 status = -EINVAL; in scu_command()
1522 mutex_unlock(&state->mutex); in scu_command()
1569 return -EINVAL; in ctrl_power_mode()
1589 return -EINVAL; in ctrl_power_mode()
1593 if (state->m_current_power_mode == *mode) in ctrl_power_mode()
1597 if (state->m_current_power_mode != DRX_POWER_UP) { in ctrl_power_mode()
1611 /* Set pins with possible pull-ups connected in ctrl_power_mode()
1618 switch (state->m_operation_mode) { in ctrl_power_mode()
1650 state->m_hi_cfg_ctrl |= in ctrl_power_mode()
1657 state->m_current_power_mode = *mode; in ctrl_power_mode()
1742 if (state->m_operation_mode == o_mode) in setoperation_mode()
1745 switch (state->m_operation_mode) { in setoperation_mode()
1756 state->m_operation_mode = OM_NONE; in setoperation_mode()
1766 state->m_operation_mode = OM_NONE; in setoperation_mode()
1770 status = -EINVAL; in setoperation_mode()
1779 dprintk(1, ": DVB-T\n"); in setoperation_mode()
1780 state->m_operation_mode = o_mode; in setoperation_mode()
1787 dprintk(1, ": DVB-C Annex %c\n", in setoperation_mode()
1788 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); in setoperation_mode()
1789 state->m_operation_mode = o_mode; in setoperation_mode()
1796 status = -EINVAL; in setoperation_mode()
1807 int status = -EINVAL; in start()
1813 if (state->m_drxk_state != DRXK_STOPPED && in start()
1814 state->m_drxk_state != DRXK_DTV_STARTED) in start()
1817 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); in start()
1820 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; in start()
1821 intermediate_frequency = -intermediate_frequency; in start()
1824 switch (state->m_operation_mode) { in start()
1831 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1844 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1865 int status = -EINVAL; in get_lock_status()
1875 switch (state->m_operation_mode) { in get_lock_status()
1886 state->m_operation_mode, __func__); in get_lock_status()
1982 /* Check insertion of the Reed-Solomon parity bytes */ in mpegts_dto_setup()
1991 if (state->m_insert_rs_byte) { in mpegts_dto_setup()
2002 if (!state->m_enable_parallel) { in mpegts_dto_setup()
2003 /* MPEG data output is serial -> set ipr_mode[0] */ in mpegts_dto_setup()
2009 max_bit_rate = state->m_dvbt_bitrate; in mpegts_dto_setup()
2012 static_clk = state->m_dvbt_static_clk; in mpegts_dto_setup()
2018 max_bit_rate = state->m_dvbc_bitrate; in mpegts_dto_setup()
2019 static_clk = state->m_dvbc_static_clk; in mpegts_dto_setup()
2022 status = -EINVAL; in mpegts_dto_setup()
2033 (avoid intra-packet gaps), in mpegts_dto_setup()
2046 dto_period = (Fsys / bitrate) - 2 in mpegts_dto_setup()
2051 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) in mpegts_dto_setup()
2056 fec_oc_dto_period -= 2; in mpegts_dto_setup()
2059 /* (commonAttr->static_clk == false) => dynamic mode */ in mpegts_dto_setup()
2115 if (state->m_invert_data) in mpegts_configure_polarity()
2118 if (state->m_invert_err) in mpegts_configure_polarity()
2121 if (state->m_invert_str) in mpegts_configure_polarity()
2124 if (state->m_invert_val) in mpegts_configure_polarity()
2127 if (state->m_invert_clk) in mpegts_configure_polarity()
2138 int status = -EINVAL; in set_agc_rf()
2147 switch (p_agc_cfg->ctrl_mode) { in set_agc_rf()
2165 if (state->m_rf_agc_pol) in set_agc_rf()
2179 data |= (~(p_agc_cfg->speed << in set_agc_rf()
2188 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; in set_agc_rf()
2190 p_if_agc_settings = &state->m_qam_if_agc_cfg; in set_agc_rf()
2192 p_if_agc_settings = &state->m_atv_if_agc_cfg; in set_agc_rf()
2194 status = -EINVAL; in set_agc_rf()
2198 /* Set TOP, only if IF-AGC is in AUTO mode */ in set_agc_rf()
2199 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { in set_agc_rf()
2202 p_agc_cfg->top); in set_agc_rf()
2207 /* Cut-Off current */ in set_agc_rf()
2209 p_agc_cfg->cut_off_current); in set_agc_rf()
2215 p_agc_cfg->max_output_level); in set_agc_rf()
2236 if (state->m_rf_agc_pol) in set_agc_rf()
2251 p_agc_cfg->output_level); in set_agc_rf()
2277 status = -EINVAL; in set_agc_rf()
2297 switch (p_agc_cfg->ctrl_mode) { in set_agc_if()
2317 if (state->m_if_agc_pol) in set_agc_if()
2330 data |= (~(p_agc_cfg->speed << in set_agc_if()
2339 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; in set_agc_if()
2341 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; in set_agc_if()
2343 return -1; in set_agc_if()
2346 p_rf_agc_settings->top); in set_agc_if()
2370 if (state->m_if_agc_pol) in set_agc_if()
2380 p_agc_cfg->output_level); in set_agc_if()
2405 } /* switch (agcSettingsIf->ctrl_mode) */ in set_agc_if()
2408 configurations without if-loop */ in set_agc_if()
2409 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); in set_agc_if()
2434 return -EINVAL; in get_qam_signal_to_noise()
2437 switch (state->props.modulation) { in get_qam_signal_to_noise()
2457 qam_sl_mer = log10times100(qam_sl_sig_power) - in get_qam_signal_to_noise()
2545 => IMER = a + b -c in get_dvbt_signal_to_noise()
2551 /* log(x) x = 9bits * 9bits->18 bits */ in get_dvbt_signal_to_noise()
2554 /* log(x) x = 16bits * 7bits->23 bits */ in get_dvbt_signal_to_noise()
2556 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ in get_dvbt_signal_to_noise()
2559 i_mer = a + b - c; in get_dvbt_signal_to_noise()
2574 switch (state->m_operation_mode) { in get_signal_to_noise()
2600 108, /* 16-QAM 1/2 */
2601 131, /* 16-QAM 2/3 */
2602 146, /* 16-QAM 3/4 */
2603 156, /* 16-QAM 5/6 */
2604 160, /* 16-QAM 7/8 */
2605 165, /* 64-QAM 1/2 */
2606 187, /* 64-QAM 2/3 */
2607 202, /* 64-QAM 3/4 */
2608 216, /* 64-QAM 5/6 */
2609 225, /* 64-QAM 7/8 */
2639 signal_to_noise_rel = signal_to_noise -
2643 if (signal_to_noise_rel < -70)
2670 switch (state->props.modulation) {
2672 signal_to_noise_rel = signal_to_noise - 200;
2675 signal_to_noise_rel = signal_to_noise - 230;
2678 signal_to_noise_rel = signal_to_noise - 260;
2681 signal_to_noise_rel = signal_to_noise - 290;
2685 signal_to_noise_rel = signal_to_noise - 320;
2689 if (signal_to_noise_rel < -70)
2705 switch (state->m_operation_mode) {
2733 int status = -EINVAL; in ConfigureI2CBridge()
2737 if (state->m_drxk_state == DRXK_UNINITIALIZED) in ConfigureI2CBridge()
2739 if (state->m_drxk_state == DRXK_POWERED_DOWN) in ConfigureI2CBridge()
2742 if (state->no_i2c_bridge) in ConfigureI2CBridge()
2772 int status = -EINVAL; in set_pre_saw()
2777 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) in set_pre_saw()
2780 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); in set_pre_saw()
2798 mutex_lock(&state->mutex); in bl_direct_cmd()
2826 status = -EINVAL; in bl_direct_cmd()
2833 mutex_unlock(&state->mutex); in bl_direct_cmd()
2913 status = -EINVAL; in adc_synchronization()
2927 bool tuner_mirror = !state->m_b_mirror_freq_spect; in set_frequency_shifter()
2932 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); in set_frequency_shifter()
2943 if ((state->m_operation_mode == OM_QAM_ITU_A) || in set_frequency_shifter()
2944 (state->m_operation_mode == OM_QAM_ITU_C) || in set_frequency_shifter()
2945 (state->m_operation_mode == OM_DVBT)) in set_frequency_shifter()
2956 if_freq_actual = intermediate_freqk_hz - in set_frequency_shifter()
2957 rf_freq_residual - fm_frequency_shift; in set_frequency_shifter()
2960 adc_freq = sampling_frequency - if_freq_actual; in set_frequency_shifter()
2969 image_to_select = state->m_rfmirror ^ tuner_mirror ^ in set_frequency_shifter()
2971 state->m_iqm_fs_rate_ofs = in set_frequency_shifter()
2975 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; in set_frequency_shifter()
2980 state->m_iqm_fs_rate_ofs); in set_frequency_shifter()
3017 pr_err("%s: mode %d is not DVB-C\n", in init_agc()
3018 __func__, state->m_operation_mode); in init_agc()
3019 return -EINVAL; in init_agc()
3026 clp_dir_to = (u16) -9; in init_agc()
3029 sns_dir_to = (u16) -9; in init_agc()
3030 ki_innergain_min = (u16) -1030; in init_agc()
3036 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; in init_agc()
3097 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); in init_agc()
3162 /* Initialize inner-loop KI gain factors */ in init_agc()
3210 status = -EINVAL; in dvbt_sc_command()
3225 /* Write sub-command */ in dvbt_sc_command()
3227 /* All commands using sub-cmd */ in dvbt_sc_command()
3263 status = -EINVAL; in dvbt_sc_command()
3282 status = -EINVAL; in dvbt_sc_command()
3308 status = -EINVAL; in dvbt_sc_command()
3310 } /* switch (cmd->cmd) */ in dvbt_sc_command()
3375 switch (echo_thres->fft_mode) { in dvbt_ctrl_set_echo_threshold()
3378 data |= ((echo_thres->threshold << in dvbt_ctrl_set_echo_threshold()
3384 data |= ((echo_thres->threshold << in dvbt_ctrl_set_echo_threshold()
3389 return -EINVAL; in dvbt_ctrl_set_echo_threshold()
3402 int status = -EINVAL; in dvbt_ctrl_set_sqi_speed()
3455 state->m_dvbt_if_agc_cfg.ingain_tgt_max); in dvbt_activate_presets()
3465 * \brief Initialize channelswitch-independent settings for DVBT.
3470 * the DVB-T taps from the drxk_filters.h are used.
3511 /* synchronize on ofdstate->m_festart */ in set_dvbt_standard()
3519 /* window size for sense pre-SAW detection */ in set_dvbt_standard()
3523 /* sense threshold for sense pre-SAW detection */ in set_dvbt_standard()
3593 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); in set_dvbt_standard()
3597 /* Halt SCU to enable safe non-atomic accesses */ in set_dvbt_standard()
3602 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); in set_dvbt_standard()
3605 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); in set_dvbt_standard()
3623 if (!state->m_drxk_a3_rom_code) { in set_dvbt_standard()
3626 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); in set_dvbt_standard()
3737 /* Halt SCU to enable safe non-atomic accesses */ in set_dvbt()
3759 switch (state->props.transmission_mode) { in set_dvbt()
3771 switch (state->props.guard_interval) { in set_dvbt()
3789 switch (state->props.hierarchy) { in set_dvbt()
3806 switch (state->props.modulation) { in set_dvbt()
3822 switch (channel->priority) { in set_dvbt()
3835 status = -EINVAL; in set_dvbt()
3847 switch (state->props.code_rate_HP) { in set_dvbt()
3880 switch (state->props.bandwidth_hz) { in set_dvbt()
3882 state->props.bandwidth_hz = 8000000; in set_dvbt()
3957 status = -EINVAL; in set_dvbt()
3963 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) in set_dvbt()
3965 ((SysFreq / BandWidth) * (2^21)) - (2^23) in set_dvbt()
3975 ((state->m_sys_clock_freq * in set_dvbt()
3981 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ in set_dvbt()
3982 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); in set_dvbt()
4037 if (!state->m_drxk_a3_rom_code) in set_dvbt()
4038 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); in set_dvbt()
4127 /* stop all comstate->m_exec */ in power_down_qam()
4196 status = -EINVAL; in set_qam_measurement()
4201 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ in set_qam_measurement()
4212 status = -EINVAL; in set_qam_measurement()
4406 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); in set_qam16()
4409 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); in set_qam16()
4412 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); in set_qam16()
4599 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); in set_qam32()
4602 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); in set_qam32()
4605 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); in set_qam32()
4608 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); in set_qam32()
4611 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); in set_qam32()
4799 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); in set_qam64()
4802 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); in set_qam64()
4805 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); in set_qam64()
4996 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); in set_qam128()
4999 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); in set_qam128()
5002 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); in set_qam128()
5198 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); in set_qam256()
5219 /* Stop QAM comstate->m_exec */ in qam_reset_qam()
5252 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; in qam_set_symbolrate()
5254 if (state->props.symbol_rate <= 1188750) in qam_set_symbolrate()
5256 else if (state->props.symbol_rate <= 2377500) in qam_set_symbolrate()
5258 else if (state->props.symbol_rate <= 4755000) in qam_set_symbolrate()
5265 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) in qam_set_symbolrate()
5267 symb_freq = state->props.symbol_rate * (1 << ratesel); in qam_set_symbolrate()
5270 status = -EINVAL; in qam_set_symbolrate()
5274 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - in qam_set_symbolrate()
5279 state->m_iqm_rc_rate = iqm_rc_rate; in qam_set_symbolrate()
5283 symb_freq = state->props.symbol_rate; in qam_set_symbolrate()
5286 status = -EINVAL; in qam_set_symbolrate()
5359 set_param_parameters[0] = state->m_constellation; /* modulation */ in qam_demodulator_command()
5365 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5383 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5401 status = -EINVAL; in qam_demodulator_command()
5415 int qam_demod_param_count = state->qam_demod_parameter_count; in set_qam()
5436 * -set params; resets IQM,QAM,FEC HW; initializes some in set_qam()
5444 switch (state->props.modulation) { in set_qam()
5446 state->m_constellation = DRX_CONSTELLATION_QAM256; in set_qam()
5450 state->m_constellation = DRX_CONSTELLATION_QAM64; in set_qam()
5453 state->m_constellation = DRX_CONSTELLATION_QAM16; in set_qam()
5456 state->m_constellation = DRX_CONSTELLATION_QAM32; in set_qam()
5459 state->m_constellation = DRX_CONSTELLATION_QAM128; in set_qam()
5462 status = -EINVAL; in set_qam()
5468 /* Use the 4-parameter if it's requested or we're probing for in set_qam()
5470 if (state->qam_demod_parameter_count == 4 in set_qam()
5471 || !state->qam_demod_parameter_count) { in set_qam()
5476 /* Use the 2-parameter command if it was requested or if we're in set_qam()
5477 * probing for the correct command and the 4-parameter command in set_qam()
5479 if (state->qam_demod_parameter_count == 2 in set_qam()
5480 || (!state->qam_demod_parameter_count && status < 0)) { in set_qam()
5489 state->qam_demod_parameter_count, in set_qam()
5490 state->microcode_name); in set_qam()
5492 } else if (!state->qam_demod_parameter_count) { in set_qam()
5494 "Auto-probing the QAM command parameters was successful - using %d parameters.\n", in set_qam()
5499 * auto-probe anymore, now that we got the correct command. in set_qam()
5501 state->qam_demod_parameter_count = qam_demod_param_count; in set_qam()
5519 status = set_qam_measurement(state, state->m_constellation, in set_qam()
5520 state->props.symbol_rate); in set_qam()
5592 /* Mirroring, QAM-block starting point not inverted */ in set_qam()
5598 /* Halt SCU to enable safe non-atomic accesses */ in set_qam()
5604 switch (state->props.modulation) { in set_qam()
5622 status = -EINVAL; in set_qam()
5633 /* Re-configure MPEG output, requires knowledge of channel bitrate */ in set_qam()
5634 /* extAttr->currentChannel.modulation = channel->modulation; */ in set_qam()
5635 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ in set_qam()
5636 status = mpegts_dto_setup(state, state->m_operation_mode); in set_qam()
5662 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ in set_qam()
5685 /* Ensure correct power-up mode */ in set_qam_standard()
5725 status = -EINVAL; in set_qam_standard()
5811 /* Halt SCU to enable safe non-atomic accesses */ in set_qam_standard()
5822 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); in set_qam_standard()
5827 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); in set_qam_standard()
5830 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); in set_qam_standard()
5859 if (state->m_has_sawsw) { in write_gpio()
5860 if (state->uio_mask & 0x0001) { /* UIO-1 */ in write_gpio()
5861 /* write to io pad configuration register - output mode */ in write_gpio()
5863 state->m_gpio_cfg); in write_gpio()
5871 if ((state->m_gpio & 0x0001) == 0) in write_gpio()
5872 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ in write_gpio()
5874 value |= 0x8000; /* write one to 15th bit - 1st UIO */ in write_gpio()
5880 if (state->uio_mask & 0x0002) { /* UIO-2 */ in write_gpio()
5881 /* write to io pad configuration register - output mode */ in write_gpio()
5883 state->m_gpio_cfg); in write_gpio()
5891 if ((state->m_gpio & 0x0002) == 0) in write_gpio()
5892 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ in write_gpio()
5894 value |= 0x4000; /* write one to 14th bit - 2st UIO */ in write_gpio()
5900 if (state->uio_mask & 0x0004) { /* UIO-3 */ in write_gpio()
5901 /* write to io pad configuration register - output mode */ in write_gpio()
5903 state->m_gpio_cfg); in write_gpio()
5911 if ((state->m_gpio & 0x0004) == 0) in write_gpio()
5912 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ in write_gpio()
5914 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ in write_gpio()
5936 if (!state->antenna_gpio) in switch_antenna_to_qam()
5939 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_qam()
5941 if (state->antenna_dvbt ^ gpio_state) { in switch_antenna_to_qam()
5942 /* Antenna is on DVB-T mode. Switch */ in switch_antenna_to_qam()
5943 if (state->antenna_dvbt) in switch_antenna_to_qam()
5944 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_qam()
5946 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_qam()
5961 if (!state->antenna_gpio) in switch_antenna_to_dvbt()
5964 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_dvbt()
5966 if (!(state->antenna_dvbt ^ gpio_state)) { in switch_antenna_to_dvbt()
5967 /* Antenna is on DVB-C mode. Switch */ in switch_antenna_to_dvbt()
5968 if (state->antenna_dvbt) in switch_antenna_to_dvbt()
5969 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_dvbt()
5971 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_dvbt()
5984 /* Set pins with possible pull-ups connected to them in input mode */ in power_down_device()
5991 if (state->m_b_p_down_open_bridge) { in power_down_device()
5992 /* Open I2C bridge before power down of DRXK */ in power_down_device()
6009 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in power_down_device()
6025 if (state->m_drxk_state == DRXK_UNINITIALIZED) { in init_drxk()
6033 /* Soft reset of OFDM-, sys- and osc-clockdomain */ in init_drxk()
6048 state->m_drxk_a3_patch_code = true; in init_drxk()
6056 state->m_hi_cfg_bridge_delay = in init_drxk()
6057 (u16) ((state->m_osc_clock_freq / 1000) * in init_drxk()
6060 if (state->m_hi_cfg_bridge_delay > in init_drxk()
6062 state->m_hi_cfg_bridge_delay = in init_drxk()
6065 /* SCL bridge delay, same as SDA for now */ in init_drxk()
6066 state->m_hi_cfg_bridge_delay += in init_drxk()
6067 state->m_hi_cfg_bridge_delay << in init_drxk()
6075 if (!(state->m_DRXK_A1_ROM_CODE) in init_drxk()
6076 && !(state->m_DRXK_A2_ROM_CODE)) in init_drxk()
6098 /* enable token-ring bus through OFDM block for possible ucode upload */ in init_drxk()
6113 if (state->fw) { in init_drxk()
6114 status = download_microcode(state, state->fw->data, in init_drxk()
6115 state->fw->size); in init_drxk()
6120 /* disable token-ring bus through OFDM block for possible ucode upload */ in init_drxk()
6200 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); in init_drxk()
6208 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6210 if (state->m_b_power_down) { in init_drxk()
6214 state->m_drxk_state = DRXK_POWERED_DOWN; in init_drxk()
6216 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6220 if (state->m_has_dvbc) { in init_drxk()
6221 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; in init_drxk()
6222 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; in init_drxk()
6223 strlcat(state->frontend.ops.info.name, " DVB-C", in init_drxk()
6224 sizeof(state->frontend.ops.info.name)); in init_drxk()
6226 if (state->m_has_dvbt) { in init_drxk()
6227 state->frontend.ops.delsys[n++] = SYS_DVBT; in init_drxk()
6228 strlcat(state->frontend.ops.info.name, " DVB-T", in init_drxk()
6229 sizeof(state->frontend.ops.info.name)); in init_drxk()
6235 state->m_drxk_state = DRXK_NO_DEV; in init_drxk()
6251 state->microcode_name); in load_firmware_cb()
6253 state->microcode_name); in load_firmware_cb()
6254 state->microcode_name = NULL; in load_firmware_cb()
6260 * We might also change all DVB callbacks to return -ENODEV in load_firmware_cb()
6262 * As the DRX-K devices have their own internal firmware, in load_firmware_cb()
6267 state->fw = fw; in load_firmware_cb()
6274 struct drxk_state *state = fe->demodulator_priv; in drxk_release()
6277 release_firmware(state->fw); in drxk_release()
6284 struct drxk_state *state = fe->demodulator_priv; in drxk_sleep()
6288 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_sleep()
6289 return -ENODEV; in drxk_sleep()
6290 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_sleep()
6299 struct drxk_state *state = fe->demodulator_priv; in drxk_gate_ctrl()
6303 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_gate_ctrl()
6304 return -ENODEV; in drxk_gate_ctrl()
6311 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drxk_set_parameters()
6312 u32 delsys = p->delivery_system, old_delsys; in drxk_set_parameters()
6313 struct drxk_state *state = fe->demodulator_priv; in drxk_set_parameters()
6318 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_set_parameters()
6319 return -ENODEV; in drxk_set_parameters()
6321 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_set_parameters()
6322 return -EAGAIN; in drxk_set_parameters()
6324 if (!fe->ops.tuner_ops.get_if_frequency) { in drxk_set_parameters()
6326 return -EINVAL; in drxk_set_parameters()
6329 if (fe->ops.i2c_gate_ctrl) in drxk_set_parameters()
6330 fe->ops.i2c_gate_ctrl(fe, 1); in drxk_set_parameters()
6331 if (fe->ops.tuner_ops.set_params) in drxk_set_parameters()
6332 fe->ops.tuner_ops.set_params(fe); in drxk_set_parameters()
6333 if (fe->ops.i2c_gate_ctrl) in drxk_set_parameters()
6334 fe->ops.i2c_gate_ctrl(fe, 0); in drxk_set_parameters()
6336 old_delsys = state->props.delivery_system; in drxk_set_parameters()
6337 state->props = *p; in drxk_set_parameters()
6344 if (!state->m_has_dvbc) in drxk_set_parameters()
6345 return -EINVAL; in drxk_set_parameters()
6346 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? in drxk_set_parameters()
6348 if (state->m_itut_annex_c) in drxk_set_parameters()
6354 if (!state->m_has_dvbt) in drxk_set_parameters()
6355 return -EINVAL; in drxk_set_parameters()
6359 return -EINVAL; in drxk_set_parameters()
6363 fe->ops.tuner_ops.get_if_frequency(fe, &IF); in drxk_set_parameters()
6367 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drxk_set_parameters()
6368 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6369 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6370 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6371 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6372 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6373 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6374 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6397 rf_agc = state->m_dvbt_rf_agc_cfg; in get_strength()
6398 if_agc = state->m_dvbt_if_agc_cfg; in get_strength()
6400 rf_agc = state->m_qam_rf_agc_cfg; in get_strength()
6401 if_agc = state->m_qam_if_agc_cfg; in get_strength()
6403 rf_agc = state->m_atv_rf_agc_cfg; in get_strength()
6404 if_agc = state->m_atv_if_agc_cfg; in get_strength()
6432 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); in get_strength()
6436 ((u32)(rf_agc.output_level - rf_agc.min_output_level)) in get_strength()
6461 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); in get_strength()
6465 ((u32)(if_agc.output_level - if_agc.min_output_level)) in get_strength()
6484 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drxk_get_stats()
6485 struct drxk_state *state = fe->demodulator_priv; in drxk_get_stats()
6498 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_stats()
6499 return -ENODEV; in drxk_get_stats()
6500 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_stats()
6501 return -EAGAIN; in drxk_get_stats()
6504 state->fe_status = 0; in drxk_get_stats()
6507 state->fe_status |= 0x1f; in drxk_get_stats()
6509 state->fe_status |= 0x0f; in drxk_get_stats()
6511 state->fe_status |= 0x07; in drxk_get_stats()
6516 get_strength(state, &c->strength.stat[0].uvalue); in drxk_get_stats()
6517 c->strength.stat[0].scale = FE_SCALE_RELATIVE; in drxk_get_stats()
6522 c->cnr.stat[0].svalue = cnr * 100; in drxk_get_stats()
6523 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; in drxk_get_stats()
6525 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6529 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6530 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6531 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6532 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6533 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6534 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6559 /* Number of bit-errors */ in drxk_get_stats()
6586 c->block_error.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6587 c->block_error.stat[0].uvalue += pkt_error_count; in drxk_get_stats()
6588 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6589 c->block_count.stat[0].uvalue += pkt_count; in drxk_get_stats()
6591 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6592 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; in drxk_get_stats()
6593 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6594 c->pre_bit_count.stat[0].uvalue += pre_bit_count; in drxk_get_stats()
6596 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6597 c->post_bit_error.stat[0].uvalue += post_bit_err_count; in drxk_get_stats()
6598 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6599 c->post_bit_count.stat[0].uvalue += post_bit_count; in drxk_get_stats()
6608 struct drxk_state *state = fe->demodulator_priv; in drxk_read_status()
6617 *status = state->fe_status; in drxk_read_status()
6625 struct drxk_state *state = fe->demodulator_priv; in drxk_read_signal_strength()
6626 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drxk_read_signal_strength()
6630 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_signal_strength()
6631 return -ENODEV; in drxk_read_signal_strength()
6632 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_signal_strength()
6633 return -EAGAIN; in drxk_read_signal_strength()
6635 *strength = c->strength.stat[0].uvalue; in drxk_read_signal_strength()
6641 struct drxk_state *state = fe->demodulator_priv; in drxk_read_snr()
6646 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_snr()
6647 return -ENODEV; in drxk_read_snr()
6648 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_snr()
6649 return -EAGAIN; in drxk_read_snr()
6662 struct drxk_state *state = fe->demodulator_priv; in drxk_read_ucblocks()
6667 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_ucblocks()
6668 return -ENODEV; in drxk_read_ucblocks()
6669 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_ucblocks()
6670 return -EAGAIN; in drxk_read_ucblocks()
6680 struct drxk_state *state = fe->demodulator_priv; in drxk_get_tune_settings()
6681 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drxk_get_tune_settings()
6685 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_tune_settings()
6686 return -ENODEV; in drxk_get_tune_settings()
6687 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_tune_settings()
6688 return -EAGAIN; in drxk_get_tune_settings()
6690 switch (p->delivery_system) { in drxk_get_tune_settings()
6694 sets->min_delay_ms = 3000; in drxk_get_tune_settings()
6695 sets->max_drift = 0; in drxk_get_tune_settings()
6696 sets->step_size = 0; in drxk_get_tune_settings()
6699 return -EINVAL; in drxk_get_tune_settings()
6709 /* For DVB-C */
6712 /* For DVB-T */
6741 u8 adr = config->adr; in drxk_attach()
6749 state->i2c = i2c; in drxk_attach()
6750 state->demod_address = adr; in drxk_attach()
6751 state->single_master = config->single_master; in drxk_attach()
6752 state->microcode_name = config->microcode_name; in drxk_attach()
6753 state->qam_demod_parameter_count = config->qam_demod_parameter_count; in drxk_attach()
6754 state->no_i2c_bridge = config->no_i2c_bridge; in drxk_attach()
6755 state->antenna_gpio = config->antenna_gpio; in drxk_attach()
6756 state->antenna_dvbt = config->antenna_dvbt; in drxk_attach()
6757 state->m_chunk_size = config->chunk_size; in drxk_attach()
6758 state->enable_merr_cfg = config->enable_merr_cfg; in drxk_attach()
6760 if (config->dynamic_clk) { in drxk_attach()
6761 state->m_dvbt_static_clk = false; in drxk_attach()
6762 state->m_dvbc_static_clk = false; in drxk_attach()
6764 state->m_dvbt_static_clk = true; in drxk_attach()
6765 state->m_dvbc_static_clk = true; in drxk_attach()
6769 if (config->mpeg_out_clk_strength) in drxk_attach()
6770 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; in drxk_attach()
6772 state->m_ts_clockk_strength = 0x06; in drxk_attach()
6774 if (config->parallel_ts) in drxk_attach()
6775 state->m_enable_parallel = true; in drxk_attach()
6777 state->m_enable_parallel = false; in drxk_attach()
6780 state->uio_mask = config->antenna_gpio; in drxk_attach()
6782 /* Default gpio to DVB-C */ in drxk_attach()
6783 if (!state->antenna_dvbt && state->antenna_gpio) in drxk_attach()
6784 state->m_gpio |= state->antenna_gpio; in drxk_attach()
6786 state->m_gpio &= ~state->antenna_gpio; in drxk_attach()
6788 mutex_init(&state->mutex); in drxk_attach()
6790 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); in drxk_attach()
6791 state->frontend.demodulator_priv = state; in drxk_attach()
6795 /* Load firmware and initialize DRX-K */ in drxk_attach()
6796 if (state->microcode_name) { in drxk_attach()
6799 status = request_firmware(&fw, state->microcode_name, in drxk_attach()
6800 state->i2c->dev.parent); in drxk_attach()
6809 p = &state->frontend.dtv_property_cache; in drxk_attach()
6810 p->strength.len = 1; in drxk_attach()
6811 p->cnr.len = 1; in drxk_attach()
6812 p->block_error.len = 1; in drxk_attach()
6813 p->block_count.len = 1; in drxk_attach()
6814 p->pre_bit_error.len = 1; in drxk_attach()
6815 p->pre_bit_count.len = 1; in drxk_attach()
6816 p->post_bit_error.len = 1; in drxk_attach()
6817 p->post_bit_count.len = 1; in drxk_attach()
6819 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drxk_attach()
6820 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6821 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6822 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6823 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6824 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6825 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6826 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6829 return &state->frontend; in drxk_attach()
6838 MODULE_DESCRIPTION("DRX-K driver");