228 	int status;  in i2c_write()  local
239 	status = drxk_i2c_transfer(state, &msg, 1);  in i2c_write()
240 	if (status >= 0 && status != 1)  in i2c_write()
241 		status = -EIO;  in i2c_write()
243 	if (status < 0)  in i2c_write()
246 	return status;  in i2c_write()
252 	int status;  in i2c_read()  local
260 	status = drxk_i2c_transfer(state, msgs, 2);  in i2c_read()
261 	if (status != 2) {  in i2c_read()
264 		if (status >= 0)  in i2c_read()
265 			status = -EIO;  in i2c_read()
268 		return status;  in i2c_read()
285 	int status;  in read16_flags()  local
303 	status = i2c_read(state, adr, mm1, len, mm2, 2);  in read16_flags()
304 	if (status < 0)  in read16_flags()
305 		return status;  in read16_flags()
319 	int status;  in read32_flags()  local
337 	status = i2c_read(state, adr, mm1, len, mm2, 4);  in read32_flags()
338 	if (status < 0)  in read32_flags()
339 		return status;  in read32_flags()
415 	int status = 0, blk_size = block_size;  in write_block()  local
451 		status = i2c_write(state, state->demod_address,  in write_block()
453 		if (status < 0) {  in write_block()
462 	return status;  in write_block()
471 	int status;  in power_up_device()  local
477 	status = i2c_read1(state, state->demod_address, &data);  in power_up_device()
478 	if (status < 0) {  in power_up_device()
481 			status = i2c_write(state, state->demod_address,  in power_up_device()
485 			if (status < 0)  in power_up_device()
487 			status = i2c_read1(state, state->demod_address,  in power_up_device()
489 		} while (status < 0 &&  in power_up_device()
491 		if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)  in power_up_device()
496 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);  in power_up_device()
497 	if (status < 0)  in power_up_device()
499 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_up_device()
500 	if (status < 0)  in power_up_device()
503 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);  in power_up_device()
504 	if (status < 0)  in power_up_device()
510 	if (status < 0)  in power_up_device()
511 		pr_err("Error %d on %s\n", status, __func__);  in power_up_device()
513 	return status;  in power_up_device()
754 	int status = 0;  in drxx_open()  local
761 	status = write16(state, SCU_RAM_GPIO__A,  in drxx_open()
763 	if (status < 0)  in drxx_open()
766 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);  in drxx_open()
767 	if (status < 0)  in drxx_open()
769 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in drxx_open()
770 	if (status < 0)  in drxx_open()
772 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);  in drxx_open()
773 	if (status < 0)  in drxx_open()
775 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);  in drxx_open()
776 	if (status < 0)  in drxx_open()
778 	status = write16(state, SIO_TOP_COMM_KEY__A, key);  in drxx_open()
780 	if (status < 0)  in drxx_open()
781 		pr_err("Error %d on %s\n", status, __func__);  in drxx_open()
782 	return status;  in drxx_open()
789 	int status;  in get_device_capabilities()  local
796 	status = write16(state, SCU_RAM_GPIO__A,  in get_device_capabilities()
798 	if (status < 0)  in get_device_capabilities()
800 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in get_device_capabilities()
801 	if (status < 0)  in get_device_capabilities()
803 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);  in get_device_capabilities()
804 	if (status < 0)  in get_device_capabilities()
806 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in get_device_capabilities()
807 	if (status < 0)  in get_device_capabilities()
834 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);  in get_device_capabilities()
835 	if (status < 0)  in get_device_capabilities()
838 	pr_info("status = 0x%08x\n", sio_top_jtagid_lo);  in get_device_capabilities()
856 		status = -EINVAL;  in get_device_capabilities()
968 		status = -EINVAL;  in get_device_capabilities()
978 	if (status < 0)  in get_device_capabilities()
979 		pr_err("Error %d on %s\n", status, __func__);  in get_device_capabilities()
982 	return status;  in get_device_capabilities()
987 	int status;  in hi_command()  local
993 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);  in hi_command()
994 	if (status < 0)  in hi_command()
1012 			status = read16(state, SIO_HI_RA_RAM_CMD__A,  in hi_command()
1014 		} while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));  in hi_command()
1015 		if (status < 0)  in hi_command()
1017 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);  in hi_command()
1020 	if (status < 0)  in hi_command()
1021 		pr_err("Error %d on %s\n", status, __func__);  in hi_command()
1023 	return status;  in hi_command()
1028 	int status;  in hi_cfg_command()  local
1034 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,  in hi_cfg_command()
1036 	if (status < 0)  in hi_cfg_command()
1038 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,  in hi_cfg_command()
1040 	if (status < 0)  in hi_cfg_command()
1042 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,  in hi_cfg_command()
1044 	if (status < 0)  in hi_cfg_command()
1046 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,  in hi_cfg_command()
1048 	if (status < 0)  in hi_cfg_command()
1050 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in hi_cfg_command()
1052 	if (status < 0)  in hi_cfg_command()
1054 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in hi_cfg_command()
1056 	if (status < 0)  in hi_cfg_command()
1058 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);  in hi_cfg_command()
1059 	if (status < 0)  in hi_cfg_command()
1065 	if (status < 0)  in hi_cfg_command()
1066 		pr_err("Error %d on %s\n", status, __func__);  in hi_cfg_command()
1067 	return status;  in hi_cfg_command()
1084 	int status;  in mpegts_configure_pins()  local
1094 	status = write16(state, SCU_RAM_GPIO__A,  in mpegts_configure_pins()
1096 	if (status < 0)  in mpegts_configure_pins()
1100 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in mpegts_configure_pins()
1101 	if (status < 0)  in mpegts_configure_pins()
1106 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);  in mpegts_configure_pins()
1107 		if (status < 0)  in mpegts_configure_pins()
1109 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);  in mpegts_configure_pins()
1110 		if (status < 0)  in mpegts_configure_pins()
1112 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);  in mpegts_configure_pins()
1113 		if (status < 0)  in mpegts_configure_pins()
1115 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);  in mpegts_configure_pins()
1116 		if (status < 0)  in mpegts_configure_pins()
1118 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);  in mpegts_configure_pins()
1119 		if (status < 0)  in mpegts_configure_pins()
1121 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1122 		if (status < 0)  in mpegts_configure_pins()
1124 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1125 		if (status < 0)  in mpegts_configure_pins()
1127 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1128 		if (status < 0)  in mpegts_configure_pins()
1130 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1131 		if (status < 0)  in mpegts_configure_pins()
1133 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1134 		if (status < 0)  in mpegts_configure_pins()
1136 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1137 		if (status < 0)  in mpegts_configure_pins()
1139 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1140 		if (status < 0)  in mpegts_configure_pins()
1151 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1152 		if (status < 0)  in mpegts_configure_pins()
1158 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);  in mpegts_configure_pins()
1159 		if (status < 0)  in mpegts_configure_pins()
1161 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);  in mpegts_configure_pins()
1162 		if (status < 0)  in mpegts_configure_pins()
1167 			status = write16(state, SIO_PDR_MD1_CFG__A,  in mpegts_configure_pins()
1169 			if (status < 0)  in mpegts_configure_pins()
1171 			status = write16(state, SIO_PDR_MD2_CFG__A,  in mpegts_configure_pins()
1173 			if (status < 0)  in mpegts_configure_pins()
1175 			status = write16(state, SIO_PDR_MD3_CFG__A,  in mpegts_configure_pins()
1177 			if (status < 0)  in mpegts_configure_pins()
1179 			status = write16(state, SIO_PDR_MD4_CFG__A,  in mpegts_configure_pins()
1181 			if (status < 0)  in mpegts_configure_pins()
1183 			status = write16(state, SIO_PDR_MD5_CFG__A,  in mpegts_configure_pins()
1185 			if (status < 0)  in mpegts_configure_pins()
1187 			status = write16(state, SIO_PDR_MD6_CFG__A,  in mpegts_configure_pins()
1189 			if (status < 0)  in mpegts_configure_pins()
1191 			status = write16(state, SIO_PDR_MD7_CFG__A,  in mpegts_configure_pins()
1193 			if (status < 0)  in mpegts_configure_pins()
1200 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1201 			if (status < 0)  in mpegts_configure_pins()
1203 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1204 			if (status < 0)  in mpegts_configure_pins()
1206 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1207 			if (status < 0)  in mpegts_configure_pins()
1209 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1210 			if (status < 0)  in mpegts_configure_pins()
1212 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1213 			if (status < 0)  in mpegts_configure_pins()
1215 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1216 			if (status < 0)  in mpegts_configure_pins()
1218 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1219 			if (status < 0)  in mpegts_configure_pins()
1222 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);  in mpegts_configure_pins()
1223 		if (status < 0)  in mpegts_configure_pins()
1225 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1226 		if (status < 0)  in mpegts_configure_pins()
1230 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);  in mpegts_configure_pins()
1231 	if (status < 0)  in mpegts_configure_pins()
1234 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in mpegts_configure_pins()
1236 	if (status < 0)  in mpegts_configure_pins()
1237 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_configure_pins()
1238 	return status;  in mpegts_configure_pins()
1252 	int status;  in bl_chain_cmd()  local
1257 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);  in bl_chain_cmd()
1258 	if (status < 0)  in bl_chain_cmd()
1260 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);  in bl_chain_cmd()
1261 	if (status < 0)  in bl_chain_cmd()
1263 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);  in bl_chain_cmd()
1264 	if (status < 0)  in bl_chain_cmd()
1266 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_chain_cmd()
1267 	if (status < 0)  in bl_chain_cmd()
1273 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_chain_cmd()
1274 		if (status < 0)  in bl_chain_cmd()
1281 		status = -EINVAL;  in bl_chain_cmd()
1285 	if (status < 0)  in bl_chain_cmd()
1286 		pr_err("Error %d on %s\n", status, __func__);  in bl_chain_cmd()
1289 	return status;  in bl_chain_cmd()
1302 	int status = 0;  in download_microcode()  local
1346 		status = write_block(state, address, block_size, p_src);  in download_microcode()
1347 		if (status < 0) {  in download_microcode()
1348 			pr_err("Error %d while loading firmware\n", status);  in download_microcode()
1354 	return status;  in download_microcode()
1359 	int status;  in dvbt_enable_ofdm_token_ring()  local
1372 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1373 	if (status >= 0 && data == desired_status) {  in dvbt_enable_ofdm_token_ring()
1374 		/* tokenring already has correct status */  in dvbt_enable_ofdm_token_ring()
1375 		return status;  in dvbt_enable_ofdm_token_ring()
1378 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);  in dvbt_enable_ofdm_token_ring()
1382 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1383 		if ((status >= 0 && data == desired_status)  in dvbt_enable_ofdm_token_ring()
1392 	return status;  in dvbt_enable_ofdm_token_ring()
1397 	int status = 0;  in mpegts_stop()  local
1404 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_stop()
1405 	if (status < 0)  in mpegts_stop()
1408 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_stop()
1409 	if (status < 0)  in mpegts_stop()
1413 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);  in mpegts_stop()
1414 	if (status < 0)  in mpegts_stop()
1417 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);  in mpegts_stop()
1420 	if (status < 0)  in mpegts_stop()
1421 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_stop()
1423 	return status;  in mpegts_stop()
1434 	int status = -EINVAL;  in scu_command()  local
1445 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1446 		return status;  in scu_command()
1468 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);  in scu_command()
1469 		if (status < 0)  in scu_command()
1474 		status = -EIO;  in scu_command()
1483 			status = read16(state, SCU_RAM_PARAM_0__A - ii,  in scu_command()
1485 			if (status < 0)  in scu_command()
1514 		status = -EINVAL;  in scu_command()
1519 	if (status < 0)  in scu_command()
1520 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1523 	return status;  in scu_command()
1529 	int status;  in set_iqm_af()  local
1534 	status = read16(state, IQM_AF_STDBY__A, &data);  in set_iqm_af()
1535 	if (status < 0)  in set_iqm_af()
1552 	status = write16(state, IQM_AF_STDBY__A, data);  in set_iqm_af()
1555 	if (status < 0)  in set_iqm_af()
1556 		pr_err("Error %d on %s\n", status, __func__);  in set_iqm_af()
1557 	return status;  in set_iqm_af()
1562 	int status = 0;  in ctrl_power_mode()  local
1598 		status = power_up_device(state);  in ctrl_power_mode()
1599 		if (status < 0)  in ctrl_power_mode()
1601 		status = dvbt_enable_ofdm_token_ring(state, true);  in ctrl_power_mode()
1602 		if (status < 0)  in ctrl_power_mode()
1620 			status = mpegts_stop(state);  in ctrl_power_mode()
1621 			if (status < 0)  in ctrl_power_mode()
1623 			status = power_down_dvbt(state, false);  in ctrl_power_mode()
1624 			if (status < 0)  in ctrl_power_mode()
1629 			status = mpegts_stop(state);  in ctrl_power_mode()
1630 			if (status < 0)  in ctrl_power_mode()
1632 			status = power_down_qam(state);  in ctrl_power_mode()
1633 			if (status < 0)  in ctrl_power_mode()
1639 		status = dvbt_enable_ofdm_token_ring(state, false);  in ctrl_power_mode()
1640 		if (status < 0)  in ctrl_power_mode()
1642 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);  in ctrl_power_mode()
1643 		if (status < 0)  in ctrl_power_mode()
1645 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in ctrl_power_mode()
1646 		if (status < 0)  in ctrl_power_mode()
1652 			status = hi_cfg_command(state);  in ctrl_power_mode()
1653 			if (status < 0)  in ctrl_power_mode()
1660 	if (status < 0)  in ctrl_power_mode()
1661 		pr_err("Error %d on %s\n", status, __func__);  in ctrl_power_mode()
1663 	return status;  in ctrl_power_mode()
1671 	int status;  in power_down_dvbt()  local
1675 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_dvbt()
1676 	if (status < 0)  in power_down_dvbt()
1680 		status = scu_command(state,  in power_down_dvbt()
1684 		if (status < 0)  in power_down_dvbt()
1687 		status = scu_command(state,  in power_down_dvbt()
1691 		if (status < 0)  in power_down_dvbt()
1696 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in power_down_dvbt()
1697 	if (status < 0)  in power_down_dvbt()
1699 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in power_down_dvbt()
1700 	if (status < 0)  in power_down_dvbt()
1702 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in power_down_dvbt()
1703 	if (status < 0)  in power_down_dvbt()
1707 	status = set_iqm_af(state, false);  in power_down_dvbt()
1708 	if (status < 0)  in power_down_dvbt()
1713 		status = ctrl_power_mode(state, &power_mode);  in power_down_dvbt()
1714 		if (status < 0)  in power_down_dvbt()
1718 	if (status < 0)  in power_down_dvbt()
1719 		pr_err("Error %d on %s\n", status, __func__);  in power_down_dvbt()
1720 	return status;  in power_down_dvbt()
1726 	int status = 0;  in setoperation_mode()  local
1736 	status = write16(state, SCU_RAM_GPIO__A,  in setoperation_mode()
1738 	if (status < 0)  in setoperation_mode()
1750 		status = mpegts_stop(state);  in setoperation_mode()
1751 		if (status < 0)  in setoperation_mode()
1753 		status = power_down_dvbt(state, true);  in setoperation_mode()
1754 		if (status < 0)  in setoperation_mode()
1760 		status = mpegts_stop(state);  in setoperation_mode()
1761 		if (status < 0)  in setoperation_mode()
1763 		status = power_down_qam(state);  in setoperation_mode()
1764 		if (status < 0)  in setoperation_mode()
1770 		status = -EINVAL;  in setoperation_mode()
1781 		status = set_dvbt_standard(state, o_mode);  in setoperation_mode()
1782 		if (status < 0)  in setoperation_mode()
1790 		status = set_qam_standard(state, o_mode);  in setoperation_mode()
1791 		if (status < 0)  in setoperation_mode()
1796 		status = -EINVAL;  in setoperation_mode()
1799 	if (status < 0)  in setoperation_mode()
1800 		pr_err("Error %d on %s\n", status, __func__);  in setoperation_mode()
1801 	return status;  in setoperation_mode()
1807 	int status = -EINVAL;  in start()  local
1828 		status = set_qam(state, i_freqk_hz, offsetk_hz);  in start()
1829 		if (status < 0)  in start()
1835 		status = mpegts_stop(state);  in start()
1836 		if (status < 0)  in start()
1838 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);  in start()
1839 		if (status < 0)  in start()
1841 		status = dvbt_start(state);  in start()
1842 		if (status < 0)  in start()
1850 	if (status < 0)  in start()
1851 		pr_err("Error %d on %s\n", status, __func__);  in start()
1852 	return status;  in start()
1865 	int status = -EINVAL;  in get_lock_status()  local
1879 		status = get_qam_lock_status(state, p_lock_status);  in get_lock_status()
1882 		status = get_dvbt_lock_status(state, p_lock_status);  in get_lock_status()
1890 	if (status < 0)  in get_lock_status()
1891 		pr_err("Error %d on %s\n", status, __func__);  in get_lock_status()
1892 	return status;  in get_lock_status()
1897 	int status;  in mpegts_start()  local
1902 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_start()
1903 	if (status < 0)  in mpegts_start()
1906 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_start()
1907 	if (status < 0)  in mpegts_start()
1909 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);  in mpegts_start()
1911 	if (status < 0)  in mpegts_start()
1912 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_start()
1913 	return status;  in mpegts_start()
1918 	int status;  in mpegts_dto_init()  local
1923 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);  in mpegts_dto_init()
1924 	if (status < 0)  in mpegts_dto_init()
1926 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);  in mpegts_dto_init()
1927 	if (status < 0)  in mpegts_dto_init()
1929 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);  in mpegts_dto_init()
1930 	if (status < 0)  in mpegts_dto_init()
1932 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);  in mpegts_dto_init()
1933 	if (status < 0)  in mpegts_dto_init()
1935 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);  in mpegts_dto_init()
1936 	if (status < 0)  in mpegts_dto_init()
1938 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);  in mpegts_dto_init()
1939 	if (status < 0)  in mpegts_dto_init()
1941 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);  in mpegts_dto_init()
1942 	if (status < 0)  in mpegts_dto_init()
1944 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);  in mpegts_dto_init()
1945 	if (status < 0)  in mpegts_dto_init()
1949 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);  in mpegts_dto_init()
1950 	if (status < 0)  in mpegts_dto_init()
1952 	status = write16(state, FEC_OC_SNC_LWM__A, 2);  in mpegts_dto_init()
1953 	if (status < 0)  in mpegts_dto_init()
1955 	status = write16(state, FEC_OC_SNC_HWM__A, 12);  in mpegts_dto_init()
1957 	if (status < 0)  in mpegts_dto_init()
1958 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_init()
1960 	return status;  in mpegts_dto_init()
1966 	int status;  in mpegts_dto_setup()  local
1983 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);  in mpegts_dto_setup()
1984 	if (status < 0)  in mpegts_dto_setup()
1986 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
1987 	if (status < 0)  in mpegts_dto_setup()
2022 		status = -EINVAL;  in mpegts_dto_setup()
2024 	if (status < 0)  in mpegts_dto_setup()
2066 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);  in mpegts_dto_setup()
2067 	if (status < 0)  in mpegts_dto_setup()
2069 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);  in mpegts_dto_setup()
2070 	if (status < 0)  in mpegts_dto_setup()
2072 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);  in mpegts_dto_setup()
2073 	if (status < 0)  in mpegts_dto_setup()
2075 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);  in mpegts_dto_setup()
2076 	if (status < 0)  in mpegts_dto_setup()
2078 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);  in mpegts_dto_setup()
2079 	if (status < 0)  in mpegts_dto_setup()
2081 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2082 	if (status < 0)  in mpegts_dto_setup()
2086 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);  in mpegts_dto_setup()
2087 	if (status < 0)  in mpegts_dto_setup()
2089 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,  in mpegts_dto_setup()
2091 	if (status < 0)  in mpegts_dto_setup()
2093 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);  in mpegts_dto_setup()
2095 	if (status < 0)  in mpegts_dto_setup()
2096 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_setup()
2097 	return status;  in mpegts_dto_setup()
2138 	int status = -EINVAL;  in set_agc_rf()  local
2150 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2151 		if (status < 0)  in set_agc_rf()
2154 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2155 		if (status < 0)  in set_agc_rf()
2157 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2158 		if (status < 0)  in set_agc_rf()
2169 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2170 		if (status < 0)  in set_agc_rf()
2174 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_rf()
2175 		if (status < 0)  in set_agc_rf()
2183 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_rf()
2184 		if (status < 0)  in set_agc_rf()
2194 			status = -EINVAL;  in set_agc_rf()
2200 			status = write16(state,  in set_agc_rf()
2203 			if (status < 0)  in set_agc_rf()
2208 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,  in set_agc_rf()
2210 		if (status < 0)  in set_agc_rf()
2214 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,  in set_agc_rf()
2216 		if (status < 0)  in set_agc_rf()
2223 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2224 		if (status < 0)  in set_agc_rf()
2227 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2228 		if (status < 0)  in set_agc_rf()
2232 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2233 		if (status < 0)  in set_agc_rf()
2240 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2241 		if (status < 0)  in set_agc_rf()
2245 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);  in set_agc_rf()
2246 		if (status < 0)  in set_agc_rf()
2250 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,  in set_agc_rf()
2252 		if (status < 0)  in set_agc_rf()
2258 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2259 		if (status < 0)  in set_agc_rf()
2262 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2263 		if (status < 0)  in set_agc_rf()
2267 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2268 		if (status < 0)  in set_agc_rf()
2271 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2272 		if (status < 0)  in set_agc_rf()
2277 		status = -EINVAL;  in set_agc_rf()
2281 	if (status < 0)  in set_agc_rf()
2282 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_rf()
2283 	return status;  in set_agc_rf()
2292 	int status = 0;  in set_agc_if()  local
2301 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2302 		if (status < 0)  in set_agc_if()
2305 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2306 		if (status < 0)  in set_agc_if()
2309 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2310 		if (status < 0)  in set_agc_if()
2321 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2322 		if (status < 0)  in set_agc_if()
2326 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_if()
2327 		if (status < 0)  in set_agc_if()
2334 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_if()
2335 		if (status < 0)  in set_agc_if()
2345 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2347 		if (status < 0)  in set_agc_if()
2354 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2355 		if (status < 0)  in set_agc_if()
2358 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2359 		if (status < 0)  in set_agc_if()
2362 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2363 		if (status < 0)  in set_agc_if()
2374 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2375 		if (status < 0)  in set_agc_if()
2379 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2381 		if (status < 0)  in set_agc_if()
2388 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2389 		if (status < 0)  in set_agc_if()
2392 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2393 		if (status < 0)  in set_agc_if()
2397 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2398 		if (status < 0)  in set_agc_if()
2401 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2402 		if (status < 0)  in set_agc_if()
2409 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);  in set_agc_if()
2411 	if (status < 0)  in set_agc_if()
2412 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_if()
2413 	return status;  in set_agc_if()
2419 	int status = 0;  in get_qam_signal_to_noise()  local
2431 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);  in get_qam_signal_to_noise()
2432 	if (status < 0) {  in get_qam_signal_to_noise()
2433 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_signal_to_noise()
2462 	return status;  in get_qam_signal_to_noise()
2468 	int status;  in get_dvbt_signal_to_noise()  local
2485 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,  in get_dvbt_signal_to_noise()
2487 	if (status < 0)  in get_dvbt_signal_to_noise()
2489 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,  in get_dvbt_signal_to_noise()
2491 	if (status < 0)  in get_dvbt_signal_to_noise()
2493 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,  in get_dvbt_signal_to_noise()
2495 	if (status < 0)  in get_dvbt_signal_to_noise()
2497 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,  in get_dvbt_signal_to_noise()
2499 	if (status < 0)  in get_dvbt_signal_to_noise()
2507 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);  in get_dvbt_signal_to_noise()
2508 	if (status < 0)  in get_dvbt_signal_to_noise()
2516 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,  in get_dvbt_signal_to_noise()
2518 	if (status < 0)  in get_dvbt_signal_to_noise()
2564 	if (status < 0)  in get_dvbt_signal_to_noise()
2565 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_signal_to_noise()
2566 	return status;  in get_dvbt_signal_to_noise()
2590 	int status = 0;
2621 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2622 		if (status < 0)
2624 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2626 		if (status < 0)
2630 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2632 		if (status < 0)
2656 	int status = 0;
2666 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2667 		if (status < 0)
2698 	return status;
2733 	int status = -EINVAL;  in ConfigureI2CBridge()  local
2745 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in ConfigureI2CBridge()
2747 	if (status < 0)  in ConfigureI2CBridge()
2750 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2752 		if (status < 0)  in ConfigureI2CBridge()
2755 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2757 		if (status < 0)  in ConfigureI2CBridge()
2761 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);  in ConfigureI2CBridge()
2764 	if (status < 0)  in ConfigureI2CBridge()
2765 		pr_err("Error %d on %s\n", status, __func__);  in ConfigureI2CBridge()
2766 	return status;  in ConfigureI2CBridge()
2772 	int status = -EINVAL;  in set_pre_saw()  local
2780 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);  in set_pre_saw()
2782 	if (status < 0)  in set_pre_saw()
2783 		pr_err("Error %d on %s\n", status, __func__);  in set_pre_saw()
2784 	return status;  in set_pre_saw()
2793 	int status;  in bl_direct_cmd()  local
2799 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);  in bl_direct_cmd()
2800 	if (status < 0)  in bl_direct_cmd()
2802 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);  in bl_direct_cmd()
2803 	if (status < 0)  in bl_direct_cmd()
2805 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);  in bl_direct_cmd()
2806 	if (status < 0)  in bl_direct_cmd()
2808 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);  in bl_direct_cmd()
2809 	if (status < 0)  in bl_direct_cmd()
2811 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);  in bl_direct_cmd()
2812 	if (status < 0)  in bl_direct_cmd()
2814 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_direct_cmd()
2815 	if (status < 0)  in bl_direct_cmd()
2820 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_direct_cmd()
2821 		if (status < 0)  in bl_direct_cmd()
2826 		status = -EINVAL;  in bl_direct_cmd()
2830 	if (status < 0)  in bl_direct_cmd()
2831 		pr_err("Error %d on %s\n", status, __func__);  in bl_direct_cmd()
2834 	return status;  in bl_direct_cmd()
2841 	int status;  in adc_sync_measurement()  local
2846 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);  in adc_sync_measurement()
2847 	if (status < 0)  in adc_sync_measurement()
2849 	status = write16(state, IQM_AF_START_LOCK__A, 1);  in adc_sync_measurement()
2850 	if (status < 0)  in adc_sync_measurement()
2854 	status = read16(state, IQM_AF_PHASE0__A, &data);  in adc_sync_measurement()
2855 	if (status < 0)  in adc_sync_measurement()
2859 	status = read16(state, IQM_AF_PHASE1__A, &data);  in adc_sync_measurement()
2860 	if (status < 0)  in adc_sync_measurement()
2864 	status = read16(state, IQM_AF_PHASE2__A, &data);  in adc_sync_measurement()
2865 	if (status < 0)  in adc_sync_measurement()
2871 	if (status < 0)  in adc_sync_measurement()
2872 		pr_err("Error %d on %s\n", status, __func__);  in adc_sync_measurement()
2873 	return status;  in adc_sync_measurement()
2879 	int status;  in adc_synchronization()  local
2883 	status = adc_sync_measurement(state, &count);  in adc_synchronization()
2884 	if (status < 0)  in adc_synchronization()
2891 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);  in adc_synchronization()
2892 		if (status < 0)  in adc_synchronization()
2904 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);  in adc_synchronization()
2905 		if (status < 0)  in adc_synchronization()
2907 		status = adc_sync_measurement(state, &count);  in adc_synchronization()
2908 		if (status < 0)  in adc_synchronization()
2913 		status = -EINVAL;  in adc_synchronization()
2915 	if (status < 0)  in adc_synchronization()
2916 		pr_err("Error %d on %s\n", status, __func__);  in adc_synchronization()
2917 	return status;  in adc_synchronization()
2930 	int status;  in set_frequency_shifter()  local
2979 	status = write32(state, IQM_FS_RATE_OFS_LO__A,  in set_frequency_shifter()
2981 	if (status < 0)  in set_frequency_shifter()
2982 		pr_err("Error %d on %s\n", status, __func__);  in set_frequency_shifter()
2983 	return status;  in set_frequency_shifter()
3005 	int status = 0;  in init_agc()  local
3038 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in init_agc()
3040 	if (status < 0)  in init_agc()
3043 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);  in init_agc()
3044 	if (status < 0)  in init_agc()
3046 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);  in init_agc()
3047 	if (status < 0)  in init_agc()
3049 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);  in init_agc()
3050 	if (status < 0)  in init_agc()
3052 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);  in init_agc()
3053 	if (status < 0)  in init_agc()
3055 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,  in init_agc()
3057 	if (status < 0)  in init_agc()
3059 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in init_agc()
3061 	if (status < 0)  in init_agc()
3063 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);  in init_agc()
3064 	if (status < 0)  in init_agc()
3066 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);  in init_agc()
3067 	if (status < 0)  in init_agc()
3069 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);  in init_agc()
3070 	if (status < 0)  in init_agc()
3072 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);  in init_agc()
3073 	if (status < 0)  in init_agc()
3075 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);  in init_agc()
3076 	if (status < 0)  in init_agc()
3078 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);  in init_agc()
3079 	if (status < 0)  in init_agc()
3082 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,  in init_agc()
3084 	if (status < 0)  in init_agc()
3086 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,  in init_agc()
3088 	if (status < 0)  in init_agc()
3090 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);  in init_agc()
3091 	if (status < 0)  in init_agc()
3094 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);  in init_agc()
3095 	if (status < 0)  in init_agc()
3097 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);  in init_agc()
3098 	if (status < 0)  in init_agc()
3100 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);  in init_agc()
3101 	if (status < 0)  in init_agc()
3104 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);  in init_agc()
3105 	if (status < 0)  in init_agc()
3107 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);  in init_agc()
3108 	if (status < 0)  in init_agc()
3110 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);  in init_agc()
3111 	if (status < 0)  in init_agc()
3113 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);  in init_agc()
3114 	if (status < 0)  in init_agc()
3116 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);  in init_agc()
3117 	if (status < 0)  in init_agc()
3119 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);  in init_agc()
3120 	if (status < 0)  in init_agc()
3122 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);  in init_agc()
3123 	if (status < 0)  in init_agc()
3125 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);  in init_agc()
3126 	if (status < 0)  in init_agc()
3128 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);  in init_agc()
3129 	if (status < 0)  in init_agc()
3131 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);  in init_agc()
3132 	if (status < 0)  in init_agc()
3134 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);  in init_agc()
3135 	if (status < 0)  in init_agc()
3137 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);  in init_agc()
3138 	if (status < 0)  in init_agc()
3140 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);  in init_agc()
3141 	if (status < 0)  in init_agc()
3143 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);  in init_agc()
3144 	if (status < 0)  in init_agc()
3146 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);  in init_agc()
3147 	if (status < 0)  in init_agc()
3149 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);  in init_agc()
3150 	if (status < 0)  in init_agc()
3152 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);  in init_agc()
3153 	if (status < 0)  in init_agc()
3155 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);  in init_agc()
3156 	if (status < 0)  in init_agc()
3158 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);  in init_agc()
3159 	if (status < 0)  in init_agc()
3163 	status = read16(state, SCU_RAM_AGC_KI__A, &data);  in init_agc()
3164 	if (status < 0)  in init_agc()
3173 	status = write16(state, SCU_RAM_AGC_KI__A, data);  in init_agc()
3175 	if (status < 0)  in init_agc()
3176 		pr_err("Error %d on %s\n", status, __func__);  in init_agc()
3177 	return status;  in init_agc()
3182 	int status;  in dvbtqam_get_acc_pkt_err()  local
3186 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in dvbtqam_get_acc_pkt_err()
3188 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,  in dvbtqam_get_acc_pkt_err()
3190 	if (status < 0)  in dvbtqam_get_acc_pkt_err()
3191 		pr_err("Error %d on %s\n", status, __func__);  in dvbtqam_get_acc_pkt_err()
3192 	return status;  in dvbtqam_get_acc_pkt_err()
3204 	int status;  in dvbt_sc_command()  local
3207 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);  in dvbt_sc_command()
3210 		status = -EINVAL;  in dvbt_sc_command()
3212 	if (status < 0)  in dvbt_sc_command()
3219 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3222 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3231 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);  in dvbt_sc_command()
3232 		if (status < 0)  in dvbt_sc_command()
3241 	status = 0;  in dvbt_sc_command()
3250 		status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);  in dvbt_sc_command()
3254 		status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);  in dvbt_sc_command()
3259 		status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);  in dvbt_sc_command()
3263 		status = -EINVAL;  in dvbt_sc_command()
3265 	if (status < 0)  in dvbt_sc_command()
3272 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3275 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3279 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);  in dvbt_sc_command()
3282 		status = -EINVAL;  in dvbt_sc_command()
3284 	if (status < 0)  in dvbt_sc_command()
3296 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));  in dvbt_sc_command()
3308 		status = -EINVAL;  in dvbt_sc_command()
3312 	if (status < 0)  in dvbt_sc_command()
3313 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_sc_command()
3314 	return status;  in dvbt_sc_command()
3320 	int status;  in power_up_dvbt()  local
3323 	status = ctrl_power_mode(state, &power_mode);  in power_up_dvbt()
3324 	if (status < 0)  in power_up_dvbt()
3325 		pr_err("Error %d on %s\n", status, __func__);  in power_up_dvbt()
3326 	return status;  in power_up_dvbt()
3331 	int status;  in dvbt_ctrl_set_inc_enable()  local
3335 		status = write16(state, IQM_CF_BYPASSDET__A, 0);  in dvbt_ctrl_set_inc_enable()
3337 		status = write16(state, IQM_CF_BYPASSDET__A, 1);  in dvbt_ctrl_set_inc_enable()
3338 	if (status < 0)  in dvbt_ctrl_set_inc_enable()
3339 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_inc_enable()
3340 	return status;  in dvbt_ctrl_set_inc_enable()
3347 	int status;  in dvbt_ctrl_set_fr_enable()  local
3352 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,  in dvbt_ctrl_set_fr_enable()
3356 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);  in dvbt_ctrl_set_fr_enable()
3358 	if (status < 0)  in dvbt_ctrl_set_fr_enable()
3359 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_fr_enable()
3361 	return status;  in dvbt_ctrl_set_fr_enable()
3368 	int status;  in dvbt_ctrl_set_echo_threshold()  local
3371 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);  in dvbt_ctrl_set_echo_threshold()
3372 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3392 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);  in dvbt_ctrl_set_echo_threshold()
3394 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3395 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_echo_threshold()
3396 	return status;  in dvbt_ctrl_set_echo_threshold()
3402 	int status = -EINVAL;  in dvbt_ctrl_set_sqi_speed()  local
3414 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,  in dvbt_ctrl_set_sqi_speed()
3417 	if (status < 0)  in dvbt_ctrl_set_sqi_speed()
3418 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_sqi_speed()
3419 	return status;  in dvbt_ctrl_set_sqi_speed()
3434 	int status;  in dvbt_activate_presets()  local
3442 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);  in dvbt_activate_presets()
3443 	if (status < 0)  in dvbt_activate_presets()
3445 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);  in dvbt_activate_presets()
3446 	if (status < 0)  in dvbt_activate_presets()
3448 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);  in dvbt_activate_presets()
3449 	if (status < 0)  in dvbt_activate_presets()
3451 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);  in dvbt_activate_presets()
3452 	if (status < 0)  in dvbt_activate_presets()
3454 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,  in dvbt_activate_presets()
3457 	if (status < 0)  in dvbt_activate_presets()
3458 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_activate_presets()
3459 	return status;  in dvbt_activate_presets()
3477 	int status;  in set_dvbt_standard()  local
3485 	status = scu_command(state,  in set_dvbt_standard()
3489 	if (status < 0)  in set_dvbt_standard()
3493 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt_standard()
3496 	if (status < 0)  in set_dvbt_standard()
3500 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt_standard()
3501 	if (status < 0)  in set_dvbt_standard()
3503 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt_standard()
3504 	if (status < 0)  in set_dvbt_standard()
3506 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_dvbt_standard()
3507 	if (status < 0)  in set_dvbt_standard()
3512 	status = write16(state, IQM_AF_UPD_SEL__A, 1);  in set_dvbt_standard()
3513 	if (status < 0)  in set_dvbt_standard()
3516 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_dvbt_standard()
3517 	if (status < 0)  in set_dvbt_standard()
3520 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_dvbt_standard()
3521 	if (status < 0)  in set_dvbt_standard()
3524 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_dvbt_standard()
3525 	if (status < 0)  in set_dvbt_standard()
3527 	status = set_iqm_af(state, true);  in set_dvbt_standard()
3528 	if (status < 0)  in set_dvbt_standard()
3531 	status = write16(state, IQM_AF_AGC_RF__A, 0);  in set_dvbt_standard()
3532 	if (status < 0)  in set_dvbt_standard()
3536 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */  in set_dvbt_standard()
3537 	if (status < 0)  in set_dvbt_standard()
3539 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */  in set_dvbt_standard()
3540 	if (status < 0)  in set_dvbt_standard()
3542 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */  in set_dvbt_standard()
3543 	if (status < 0)  in set_dvbt_standard()
3546 	status = write16(state, IQM_RC_STRETCH__A, 16);  in set_dvbt_standard()
3547 	if (status < 0)  in set_dvbt_standard()
3549 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */  in set_dvbt_standard()
3550 	if (status < 0)  in set_dvbt_standard()
3552 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */  in set_dvbt_standard()
3553 	if (status < 0)  in set_dvbt_standard()
3555 	status = write16(state, IQM_CF_SCALE__A, 1600);  in set_dvbt_standard()
3556 	if (status < 0)  in set_dvbt_standard()
3558 	status = write16(state, IQM_CF_SCALE_SH__A, 0);  in set_dvbt_standard()
3559 	if (status < 0)  in set_dvbt_standard()
3563 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_dvbt_standard()
3564 	if (status < 0)  in set_dvbt_standard()
3566 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */  in set_dvbt_standard()
3567 	if (status < 0)  in set_dvbt_standard()
3570 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,  in set_dvbt_standard()
3572 	if (status < 0)  in set_dvbt_standard()
3575 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */  in set_dvbt_standard()
3576 	if (status < 0)  in set_dvbt_standard()
3578 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);  in set_dvbt_standard()
3579 	if (status < 0)  in set_dvbt_standard()
3582 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);  in set_dvbt_standard()
3583 	if (status < 0)  in set_dvbt_standard()
3585 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_dvbt_standard()
3586 	if (status < 0)  in set_dvbt_standard()
3590 	status = adc_synchronization(state);  in set_dvbt_standard()
3591 	if (status < 0)  in set_dvbt_standard()
3593 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);  in set_dvbt_standard()
3594 	if (status < 0)  in set_dvbt_standard()
3598 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt_standard()
3599 	if (status < 0)  in set_dvbt_standard()
3602 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);  in set_dvbt_standard()
3603 	if (status < 0)  in set_dvbt_standard()
3605 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);  in set_dvbt_standard()
3606 	if (status < 0)  in set_dvbt_standard()
3610 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);  in set_dvbt_standard()
3611 	if (status < 0)  in set_dvbt_standard()
3614 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);  in set_dvbt_standard()
3615 	if (status < 0)  in set_dvbt_standard()
3619 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt_standard()
3620 	if (status < 0)  in set_dvbt_standard()
3625 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in set_dvbt_standard()
3627 		if (status < 0)  in set_dvbt_standard()
3633 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);  in set_dvbt_standard()
3634 	if (status < 0)  in set_dvbt_standard()
3636 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);  in set_dvbt_standard()
3637 	if (status < 0)  in set_dvbt_standard()
3642 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */  in set_dvbt_standard()
3643 	if (status < 0)  in set_dvbt_standard()
3648 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);  in set_dvbt_standard()
3649 	if (status < 0)  in set_dvbt_standard()
3652 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);  in set_dvbt_standard()
3653 	if (status < 0)  in set_dvbt_standard()
3656 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);  in set_dvbt_standard()
3657 	if (status < 0)  in set_dvbt_standard()
3661 	status = mpegts_dto_setup(state, OM_DVBT);  in set_dvbt_standard()
3662 	if (status < 0)  in set_dvbt_standard()
3665 	status = dvbt_activate_presets(state);  in set_dvbt_standard()
3666 	if (status < 0)  in set_dvbt_standard()
3670 	if (status < 0)  in set_dvbt_standard()
3671 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt_standard()
3672 	return status;  in set_dvbt_standard()
3684 	int status;  in dvbt_start()  local
3691 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,  in dvbt_start()
3694 	if (status < 0)  in dvbt_start()
3697 	status = mpegts_start(state);  in dvbt_start()
3698 	if (status < 0)  in dvbt_start()
3700 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in dvbt_start()
3701 	if (status < 0)  in dvbt_start()
3704 	if (status < 0)  in dvbt_start()
3705 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_start()
3706 	return status;  in dvbt_start()
3726 	int status;  in set_dvbt()  local
3731 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
3734 	if (status < 0)  in set_dvbt()
3738 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt()
3739 	if (status < 0)  in set_dvbt()
3743 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt()
3744 	if (status < 0)  in set_dvbt()
3746 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt()
3747 	if (status < 0)  in set_dvbt()
3752 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);  in set_dvbt()
3753 	if (status < 0)  in set_dvbt()
3835 		status = -EINVAL;  in set_dvbt()
3841 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);  in set_dvbt()
3842 	if (status < 0)  in set_dvbt()
3886 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3888 		if (status < 0)  in set_dvbt()
3891 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3893 		if (status < 0)  in set_dvbt()
3895 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3897 		if (status < 0)  in set_dvbt()
3899 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3901 		if (status < 0)  in set_dvbt()
3903 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3905 		if (status < 0)  in set_dvbt()
3910 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3912 		if (status < 0)  in set_dvbt()
3915 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3917 		if (status < 0)  in set_dvbt()
3919 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3921 		if (status < 0)  in set_dvbt()
3923 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3925 		if (status < 0)  in set_dvbt()
3927 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3929 		if (status < 0)  in set_dvbt()
3934 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3936 		if (status < 0)  in set_dvbt()
3939 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3941 		if (status < 0)  in set_dvbt()
3943 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3945 		if (status < 0)  in set_dvbt()
3947 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3949 		if (status < 0)  in set_dvbt()
3951 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3953 		if (status < 0)  in set_dvbt()
3957 		status = -EINVAL;  in set_dvbt()
3988 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);  in set_dvbt()
3989 	if (status < 0)  in set_dvbt()
3995 	status = dvbt_set_frequency_shift(demod, channel, tuner_offset);  in set_dvbt()
3996 	if (status < 0)  in set_dvbt()
3999 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_dvbt()
4001 	if (status < 0)  in set_dvbt()
4007 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt()
4008 	if (status < 0)  in set_dvbt()
4012 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);  in set_dvbt()
4013 	if (status < 0)  in set_dvbt()
4015 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);  in set_dvbt()
4016 	if (status < 0)  in set_dvbt()
4020 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
4023 	if (status < 0)  in set_dvbt()
4032 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,  in set_dvbt()
4034 	if (status < 0)  in set_dvbt()
4038 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);  in set_dvbt()
4040 	if (status < 0)  in set_dvbt()
4041 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt()
4043 	return status;  in set_dvbt()
4050 * \brief Retrieve lock status .
4052 * \param lockStat Pointer to lock status structure.
4058 	int status;  in get_dvbt_lock_status()  local
4072 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);  in get_dvbt_lock_status()
4073 	if (status < 0)  in get_dvbt_lock_status()
4078 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);  in get_dvbt_lock_status()
4079 	if (status < 0)  in get_dvbt_lock_status()
4091 	if (status < 0)  in get_dvbt_lock_status()
4092 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_lock_status()
4094 	return status;  in get_dvbt_lock_status()
4100 	int status;  in power_up_qam()  local
4103 	status = ctrl_power_mode(state, &power_mode);  in power_up_qam()
4104 	if (status < 0)  in power_up_qam()
4105 		pr_err("Error %d on %s\n", status, __func__);  in power_up_qam()
4107 	return status;  in power_up_qam()
4116 	int status = 0;  in power_down_qam()  local
4119 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_qam()
4120 	if (status < 0)  in power_down_qam()
4128 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in power_down_qam()
4129 		if (status < 0)  in power_down_qam()
4131 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in power_down_qam()
4134 		if (status < 0)  in power_down_qam()
4138 	status = set_iqm_af(state, false);  in power_down_qam()
4141 	if (status < 0)  in power_down_qam()
4142 		pr_err("Error %d on %s\n", status, __func__);  in power_down_qam()
4144 	return status;  in power_down_qam()
4168 	int status = 0;  in set_qam_measurement()  local
4196 		status = -EINVAL;  in set_qam_measurement()
4198 	if (status < 0)  in set_qam_measurement()
4212 		status = -EINVAL;  in set_qam_measurement()
4213 		if (status < 0)  in set_qam_measurement()
4221 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4222 	if (status < 0)  in set_qam_measurement()
4224 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,  in set_qam_measurement()
4226 	if (status < 0)  in set_qam_measurement()
4228 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4230 	if (status < 0)  in set_qam_measurement()
4231 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_measurement()
4232 	return status;  in set_qam_measurement()
4237 	int status = 0;  in set_qam16()  local
4242 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);  in set_qam16()
4243 	if (status < 0)  in set_qam16()
4245 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);  in set_qam16()
4246 	if (status < 0)  in set_qam16()
4248 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);  in set_qam16()
4249 	if (status < 0)  in set_qam16()
4251 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);  in set_qam16()
4252 	if (status < 0)  in set_qam16()
4254 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);  in set_qam16()
4255 	if (status < 0)  in set_qam16()
4257 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);  in set_qam16()
4258 	if (status < 0)  in set_qam16()
4261 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);  in set_qam16()
4262 	if (status < 0)  in set_qam16()
4264 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);  in set_qam16()
4265 	if (status < 0)  in set_qam16()
4267 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);  in set_qam16()
4268 	if (status < 0)  in set_qam16()
4270 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);  in set_qam16()
4271 	if (status < 0)  in set_qam16()
4273 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);  in set_qam16()
4274 	if (status < 0)  in set_qam16()
4276 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam16()
4277 	if (status < 0)  in set_qam16()
4280 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam16()
4281 	if (status < 0)  in set_qam16()
4283 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam16()
4284 	if (status < 0)  in set_qam16()
4286 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam16()
4287 	if (status < 0)  in set_qam16()
4291 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam16()
4293 	if (status < 0)  in set_qam16()
4297 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam16()
4298 	if (status < 0)  in set_qam16()
4300 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam16()
4301 	if (status < 0)  in set_qam16()
4303 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam16()
4304 	if (status < 0)  in set_qam16()
4306 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam16()
4307 	if (status < 0)  in set_qam16()
4309 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam16()
4310 	if (status < 0)  in set_qam16()
4312 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam16()
4313 	if (status < 0)  in set_qam16()
4315 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam16()
4316 	if (status < 0)  in set_qam16()
4318 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam16()
4319 	if (status < 0)  in set_qam16()
4322 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam16()
4323 	if (status < 0)  in set_qam16()
4325 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam16()
4326 	if (status < 0)  in set_qam16()
4328 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam16()
4329 	if (status < 0)  in set_qam16()
4331 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam16()
4332 	if (status < 0)  in set_qam16()
4334 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam16()
4335 	if (status < 0)  in set_qam16()
4337 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam16()
4338 	if (status < 0)  in set_qam16()
4340 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam16()
4341 	if (status < 0)  in set_qam16()
4343 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam16()
4344 	if (status < 0)  in set_qam16()
4346 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);  in set_qam16()
4347 	if (status < 0)  in set_qam16()
4349 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam16()
4350 	if (status < 0)  in set_qam16()
4352 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam16()
4353 	if (status < 0)  in set_qam16()
4355 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam16()
4356 	if (status < 0)  in set_qam16()
4362 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);  in set_qam16()
4363 	if (status < 0)  in set_qam16()
4365 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam16()
4366 	if (status < 0)  in set_qam16()
4368 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);  in set_qam16()
4369 	if (status < 0)  in set_qam16()
4371 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);  in set_qam16()
4372 	if (status < 0)  in set_qam16()
4374 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);  in set_qam16()
4375 	if (status < 0)  in set_qam16()
4377 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);  in set_qam16()
4378 	if (status < 0)  in set_qam16()
4381 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam16()
4382 	if (status < 0)  in set_qam16()
4384 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam16()
4385 	if (status < 0)  in set_qam16()
4387 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);  in set_qam16()
4388 	if (status < 0)  in set_qam16()
4394 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);  in set_qam16()
4395 	if (status < 0)  in set_qam16()
4397 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);  in set_qam16()
4398 	if (status < 0)  in set_qam16()
4400 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);  in set_qam16()
4401 	if (status < 0)  in set_qam16()
4403 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);  in set_qam16()
4404 	if (status < 0)  in set_qam16()
4406 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);  in set_qam16()
4407 	if (status < 0)  in set_qam16()
4409 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);  in set_qam16()
4410 	if (status < 0)  in set_qam16()
4412 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);  in set_qam16()
4413 	if (status < 0)  in set_qam16()
4417 	if (status < 0)  in set_qam16()
4418 		pr_err("Error %d on %s\n", status, __func__);  in set_qam16()
4419 	return status;  in set_qam16()
4431 	int status = 0;  in set_qam32()  local
4437 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);  in set_qam32()
4438 	if (status < 0)  in set_qam32()
4440 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);  in set_qam32()
4441 	if (status < 0)  in set_qam32()
4443 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);  in set_qam32()
4444 	if (status < 0)  in set_qam32()
4446 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);  in set_qam32()
4447 	if (status < 0)  in set_qam32()
4449 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);  in set_qam32()
4450 	if (status < 0)  in set_qam32()
4452 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);  in set_qam32()
4453 	if (status < 0)  in set_qam32()
4457 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);  in set_qam32()
4458 	if (status < 0)  in set_qam32()
4460 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);  in set_qam32()
4461 	if (status < 0)  in set_qam32()
4463 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);  in set_qam32()
4464 	if (status < 0)  in set_qam32()
4466 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);  in set_qam32()
4467 	if (status < 0)  in set_qam32()
4469 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam32()
4470 	if (status < 0)  in set_qam32()
4472 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam32()
4473 	if (status < 0)  in set_qam32()
4476 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam32()
4477 	if (status < 0)  in set_qam32()
4479 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam32()
4480 	if (status < 0)  in set_qam32()
4482 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam32()
4483 	if (status < 0)  in set_qam32()
4488 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam32()
4490 	if (status < 0)  in set_qam32()
4496 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam32()
4497 	if (status < 0)  in set_qam32()
4499 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam32()
4500 	if (status < 0)  in set_qam32()
4502 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam32()
4503 	if (status < 0)  in set_qam32()
4505 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam32()
4506 	if (status < 0)  in set_qam32()
4508 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam32()
4509 	if (status < 0)  in set_qam32()
4511 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam32()
4512 	if (status < 0)  in set_qam32()
4514 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam32()
4515 	if (status < 0)  in set_qam32()
4517 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam32()
4518 	if (status < 0)  in set_qam32()
4521 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam32()
4522 	if (status < 0)  in set_qam32()
4524 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam32()
4525 	if (status < 0)  in set_qam32()
4527 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam32()
4528 	if (status < 0)  in set_qam32()
4530 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam32()
4531 	if (status < 0)  in set_qam32()
4533 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam32()
4534 	if (status < 0)  in set_qam32()
4536 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam32()
4537 	if (status < 0)  in set_qam32()
4539 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam32()
4540 	if (status < 0)  in set_qam32()
4542 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam32()
4543 	if (status < 0)  in set_qam32()
4545 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);  in set_qam32()
4546 	if (status < 0)  in set_qam32()
4548 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam32()
4549 	if (status < 0)  in set_qam32()
4551 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam32()
4552 	if (status < 0)  in set_qam32()
4554 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam32()
4555 	if (status < 0)  in set_qam32()
4561 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);  in set_qam32()
4562 	if (status < 0)  in set_qam32()
4564 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam32()
4565 	if (status < 0)  in set_qam32()
4567 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam32()
4568 	if (status < 0)  in set_qam32()
4570 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam32()
4571 	if (status < 0)  in set_qam32()
4573 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);  in set_qam32()
4574 	if (status < 0)  in set_qam32()
4576 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam32()
4577 	if (status < 0)  in set_qam32()
4580 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam32()
4581 	if (status < 0)  in set_qam32()
4583 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam32()
4584 	if (status < 0)  in set_qam32()
4586 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);  in set_qam32()
4587 	if (status < 0)  in set_qam32()
4593 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam32()
4594 	if (status < 0)  in set_qam32()
4596 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);  in set_qam32()
4597 	if (status < 0)  in set_qam32()
4599 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);  in set_qam32()
4600 	if (status < 0)  in set_qam32()
4602 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);  in set_qam32()
4603 	if (status < 0)  in set_qam32()
4605 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);  in set_qam32()
4606 	if (status < 0)  in set_qam32()
4608 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);  in set_qam32()
4609 	if (status < 0)  in set_qam32()
4611 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);  in set_qam32()
4613 	if (status < 0)  in set_qam32()
4614 		pr_err("Error %d on %s\n", status, __func__);  in set_qam32()
4615 	return status;  in set_qam32()
4627 	int status = 0;  in set_qam64()  local
4632 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);  in set_qam64()
4633 	if (status < 0)  in set_qam64()
4635 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);  in set_qam64()
4636 	if (status < 0)  in set_qam64()
4638 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);  in set_qam64()
4639 	if (status < 0)  in set_qam64()
4641 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);  in set_qam64()
4642 	if (status < 0)  in set_qam64()
4644 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);  in set_qam64()
4645 	if (status < 0)  in set_qam64()
4647 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);  in set_qam64()
4648 	if (status < 0)  in set_qam64()
4652 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);  in set_qam64()
4653 	if (status < 0)  in set_qam64()
4655 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);  in set_qam64()
4656 	if (status < 0)  in set_qam64()
4658 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);  in set_qam64()
4659 	if (status < 0)  in set_qam64()
4661 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);  in set_qam64()
4662 	if (status < 0)  in set_qam64()
4664 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam64()
4665 	if (status < 0)  in set_qam64()
4667 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam64()
4668 	if (status < 0)  in set_qam64()
4671 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam64()
4672 	if (status < 0)  in set_qam64()
4674 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam64()
4675 	if (status < 0)  in set_qam64()
4677 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam64()
4678 	if (status < 0)  in set_qam64()
4682 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam64()
4684 	if (status < 0)  in set_qam64()
4690 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam64()
4691 	if (status < 0)  in set_qam64()
4693 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam64()
4694 	if (status < 0)  in set_qam64()
4696 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam64()
4697 	if (status < 0)  in set_qam64()
4699 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam64()
4700 	if (status < 0)  in set_qam64()
4702 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam64()
4703 	if (status < 0)  in set_qam64()
4705 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam64()
4706 	if (status < 0)  in set_qam64()
4708 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam64()
4709 	if (status < 0)  in set_qam64()
4711 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam64()
4712 	if (status < 0)  in set_qam64()
4715 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam64()
4716 	if (status < 0)  in set_qam64()
4718 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);  in set_qam64()
4719 	if (status < 0)  in set_qam64()
4721 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);  in set_qam64()
4722 	if (status < 0)  in set_qam64()
4724 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam64()
4725 	if (status < 0)  in set_qam64()
4727 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);  in set_qam64()
4728 	if (status < 0)  in set_qam64()
4730 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam64()
4731 	if (status < 0)  in set_qam64()
4733 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam64()
4734 	if (status < 0)  in set_qam64()
4736 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam64()
4737 	if (status < 0)  in set_qam64()
4739 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam64()
4740 	if (status < 0)  in set_qam64()
4742 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam64()
4743 	if (status < 0)  in set_qam64()
4745 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam64()
4746 	if (status < 0)  in set_qam64()
4748 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam64()
4749 	if (status < 0)  in set_qam64()
4755 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);  in set_qam64()
4756 	if (status < 0)  in set_qam64()
4758 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam64()
4759 	if (status < 0)  in set_qam64()
4761 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam64()
4762 	if (status < 0)  in set_qam64()
4764 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);  in set_qam64()
4765 	if (status < 0)  in set_qam64()
4767 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);  in set_qam64()
4768 	if (status < 0)  in set_qam64()
4770 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);  in set_qam64()
4771 	if (status < 0)  in set_qam64()
4774 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam64()
4775 	if (status < 0)  in set_qam64()
4777 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam64()
4778 	if (status < 0)  in set_qam64()
4780 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);  in set_qam64()
4781 	if (status < 0)  in set_qam64()
4787 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam64()
4788 	if (status < 0)  in set_qam64()
4790 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);  in set_qam64()
4791 	if (status < 0)  in set_qam64()
4793 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);  in set_qam64()
4794 	if (status < 0)  in set_qam64()
4796 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);  in set_qam64()
4797 	if (status < 0)  in set_qam64()
4799 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);  in set_qam64()
4800 	if (status < 0)  in set_qam64()
4802 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);  in set_qam64()
4803 	if (status < 0)  in set_qam64()
4805 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);  in set_qam64()
4807 	if (status < 0)  in set_qam64()
4808 		pr_err("Error %d on %s\n", status, __func__);  in set_qam64()
4810 	return status;  in set_qam64()
4822 	int status = 0;  in set_qam128()  local
4827 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);  in set_qam128()
4828 	if (status < 0)  in set_qam128()
4830 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);  in set_qam128()
4831 	if (status < 0)  in set_qam128()
4833 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);  in set_qam128()
4834 	if (status < 0)  in set_qam128()
4836 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);  in set_qam128()
4837 	if (status < 0)  in set_qam128()
4839 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);  in set_qam128()
4840 	if (status < 0)  in set_qam128()
4842 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);  in set_qam128()
4843 	if (status < 0)  in set_qam128()
4847 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);  in set_qam128()
4848 	if (status < 0)  in set_qam128()
4850 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);  in set_qam128()
4851 	if (status < 0)  in set_qam128()
4853 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);  in set_qam128()
4854 	if (status < 0)  in set_qam128()
4856 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);  in set_qam128()
4857 	if (status < 0)  in set_qam128()
4859 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);  in set_qam128()
4860 	if (status < 0)  in set_qam128()
4862 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam128()
4863 	if (status < 0)  in set_qam128()
4866 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam128()
4867 	if (status < 0)  in set_qam128()
4869 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam128()
4870 	if (status < 0)  in set_qam128()
4872 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam128()
4873 	if (status < 0)  in set_qam128()
4879 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam128()
4881 	if (status < 0)  in set_qam128()
4887 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam128()
4888 	if (status < 0)  in set_qam128()
4890 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam128()
4891 	if (status < 0)  in set_qam128()
4893 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam128()
4894 	if (status < 0)  in set_qam128()
4896 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam128()
4897 	if (status < 0)  in set_qam128()
4899 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam128()
4900 	if (status < 0)  in set_qam128()
4902 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam128()
4903 	if (status < 0)  in set_qam128()
4905 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam128()
4906 	if (status < 0)  in set_qam128()
4908 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam128()
4909 	if (status < 0)  in set_qam128()
4912 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam128()
4913 	if (status < 0)  in set_qam128()
4915 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);  in set_qam128()
4916 	if (status < 0)  in set_qam128()
4918 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);  in set_qam128()
4919 	if (status < 0)  in set_qam128()
4921 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam128()
4922 	if (status < 0)  in set_qam128()
4924 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);  in set_qam128()
4925 	if (status < 0)  in set_qam128()
4927 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);  in set_qam128()
4928 	if (status < 0)  in set_qam128()
4930 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam128()
4931 	if (status < 0)  in set_qam128()
4933 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam128()
4934 	if (status < 0)  in set_qam128()
4936 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);  in set_qam128()
4937 	if (status < 0)  in set_qam128()
4939 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam128()
4940 	if (status < 0)  in set_qam128()
4942 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam128()
4943 	if (status < 0)  in set_qam128()
4945 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam128()
4946 	if (status < 0)  in set_qam128()
4952 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam128()
4953 	if (status < 0)  in set_qam128()
4955 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam128()
4956 	if (status < 0)  in set_qam128()
4958 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam128()
4959 	if (status < 0)  in set_qam128()
4961 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam128()
4962 	if (status < 0)  in set_qam128()
4964 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);  in set_qam128()
4965 	if (status < 0)  in set_qam128()
4967 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam128()
4968 	if (status < 0)  in set_qam128()
4971 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam128()
4972 	if (status < 0)  in set_qam128()
4974 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);  in set_qam128()
4975 	if (status < 0)  in set_qam128()
4978 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam128()
4979 	if (status < 0)  in set_qam128()
4984 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam128()
4985 	if (status < 0)  in set_qam128()
4987 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);  in set_qam128()
4988 	if (status < 0)  in set_qam128()
4990 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);  in set_qam128()
4991 	if (status < 0)  in set_qam128()
4993 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);  in set_qam128()
4994 	if (status < 0)  in set_qam128()
4996 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);  in set_qam128()
4997 	if (status < 0)  in set_qam128()
4999 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);  in set_qam128()
5000 	if (status < 0)  in set_qam128()
5002 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);  in set_qam128()
5004 	if (status < 0)  in set_qam128()
5005 		pr_err("Error %d on %s\n", status, __func__);  in set_qam128()
5007 	return status;  in set_qam128()
5019 	int status = 0;  in set_qam256()  local
5024 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);  in set_qam256()
5025 	if (status < 0)  in set_qam256()
5027 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);  in set_qam256()
5028 	if (status < 0)  in set_qam256()
5030 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);  in set_qam256()
5031 	if (status < 0)  in set_qam256()
5033 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);  in set_qam256()
5034 	if (status < 0)  in set_qam256()
5036 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);  in set_qam256()
5037 	if (status < 0)  in set_qam256()
5039 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);  in set_qam256()
5040 	if (status < 0)  in set_qam256()
5044 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);  in set_qam256()
5045 	if (status < 0)  in set_qam256()
5047 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);  in set_qam256()
5048 	if (status < 0)  in set_qam256()
5050 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);  in set_qam256()
5051 	if (status < 0)  in set_qam256()
5053 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);  in set_qam256()
5054 	if (status < 0)  in set_qam256()
5056 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);  in set_qam256()
5057 	if (status < 0)  in set_qam256()
5059 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam256()
5060 	if (status < 0)  in set_qam256()
5063 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam256()
5064 	if (status < 0)  in set_qam256()
5066 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam256()
5067 	if (status < 0)  in set_qam256()
5069 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam256()
5070 	if (status < 0)  in set_qam256()
5075 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam256()
5077 	if (status < 0)  in set_qam256()
5083 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam256()
5084 	if (status < 0)  in set_qam256()
5086 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam256()
5087 	if (status < 0)  in set_qam256()
5089 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam256()
5090 	if (status < 0)  in set_qam256()
5092 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam256()
5093 	if (status < 0)  in set_qam256()
5095 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam256()
5096 	if (status < 0)  in set_qam256()
5098 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam256()
5099 	if (status < 0)  in set_qam256()
5101 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam256()
5102 	if (status < 0)  in set_qam256()
5104 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam256()
5105 	if (status < 0)  in set_qam256()
5108 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam256()
5109 	if (status < 0)  in set_qam256()
5111 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);  in set_qam256()
5112 	if (status < 0)  in set_qam256()
5114 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);  in set_qam256()
5115 	if (status < 0)  in set_qam256()
5117 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam256()
5118 	if (status < 0)  in set_qam256()
5120 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);  in set_qam256()
5121 	if (status < 0)  in set_qam256()
5123 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);  in set_qam256()
5124 	if (status < 0)  in set_qam256()
5126 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam256()
5127 	if (status < 0)  in set_qam256()
5129 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam256()
5130 	if (status < 0)  in set_qam256()
5132 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam256()
5133 	if (status < 0)  in set_qam256()
5135 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam256()
5136 	if (status < 0)  in set_qam256()
5138 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam256()
5139 	if (status < 0)  in set_qam256()
5141 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam256()
5142 	if (status < 0)  in set_qam256()
5148 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam256()
5149 	if (status < 0)  in set_qam256()
5151 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam256()
5152 	if (status < 0)  in set_qam256()
5154 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam256()
5155 	if (status < 0)  in set_qam256()
5157 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam256()
5158 	if (status < 0)  in set_qam256()
5160 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);  in set_qam256()
5161 	if (status < 0)  in set_qam256()
5163 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);  in set_qam256()
5164 	if (status < 0)  in set_qam256()
5167 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam256()
5168 	if (status < 0)  in set_qam256()
5170 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam256()
5171 	if (status < 0)  in set_qam256()
5173 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam256()
5174 	if (status < 0)  in set_qam256()
5180 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam256()
5181 	if (status < 0)  in set_qam256()
5183 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);  in set_qam256()
5184 	if (status < 0)  in set_qam256()
5186 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);  in set_qam256()
5187 	if (status < 0)  in set_qam256()
5189 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);  in set_qam256()
5190 	if (status < 0)  in set_qam256()
5192 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);  in set_qam256()
5193 	if (status < 0)  in set_qam256()
5195 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);  in set_qam256()
5196 	if (status < 0)  in set_qam256()
5198 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);  in set_qam256()
5200 	if (status < 0)  in set_qam256()
5201 		pr_err("Error %d on %s\n", status, __func__);  in set_qam256()
5202 	return status;  in set_qam256()
5215 	int status;  in qam_reset_qam()  local
5220 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in qam_reset_qam()
5221 	if (status < 0)  in qam_reset_qam()
5224 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in qam_reset_qam()
5228 	if (status < 0)  in qam_reset_qam()
5229 		pr_err("Error %d on %s\n", status, __func__);  in qam_reset_qam()
5230 	return status;  in qam_reset_qam()
5248 	int status;  in qam_set_symbolrate()  local
5260 	status = write16(state, IQM_FD_RATESEL__A, ratesel);  in qam_set_symbolrate()
5261 	if (status < 0)  in qam_set_symbolrate()
5270 		status = -EINVAL;  in qam_set_symbolrate()
5276 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);  in qam_set_symbolrate()
5277 	if (status < 0)  in qam_set_symbolrate()
5286 		status = -EINVAL;  in qam_set_symbolrate()
5294 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);  in qam_set_symbolrate()
5297 	if (status < 0)  in qam_set_symbolrate()
5298 		pr_err("Error %d on %s\n", status, __func__);  in qam_set_symbolrate()
5299 	return status;  in qam_set_symbolrate()
5305 * \brief Get QAM lock status.
5313 	int status;  in get_qam_lock_status()  local
5318 	status = scu_command(state,  in get_qam_lock_status()
5322 	if (status < 0)  in get_qam_lock_status()
5323 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_lock_status()
5342 	return status;  in get_qam_lock_status()
5355 	int status;  in qam_demodulator_command()  local
5370 		status = scu_command(state,  in qam_demodulator_command()
5374 		if (status < 0)  in qam_demodulator_command()
5377 		status = scu_command(state,  in qam_demodulator_command()
5393 		status = scu_command(state,  in qam_demodulator_command()
5401 		status = -EINVAL;  in qam_demodulator_command()
5405 	if (status < 0)  in qam_demodulator_command()
5406 		pr_warn("Warning %d on %s\n", status, __func__);  in qam_demodulator_command()
5407 	return status;  in qam_demodulator_command()
5413 	int status;  in set_qam()  local
5424 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);  in set_qam()
5425 	if (status < 0)  in set_qam()
5427 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);  in set_qam()
5428 	if (status < 0)  in set_qam()
5430 	status = qam_reset_qam(state);  in set_qam()
5431 	if (status < 0)  in set_qam()
5439 	status = qam_set_symbolrate(state);  in set_qam()
5440 	if (status < 0)  in set_qam()
5462 		status = -EINVAL;  in set_qam()
5465 	if (status < 0)  in set_qam()
5473 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5480 		|| (!state->qam_demod_parameter_count && status < 0)) {  in set_qam()
5482 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5485 	if (status < 0) {  in set_qam()
5509 	status = set_frequency(channel, tuner_freq_offset));  in set_qam()
5510 	if (status < 0)  in set_qam()
5513 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_qam()
5515 	if (status < 0)  in set_qam()
5519 	status = set_qam_measurement(state, state->m_constellation,  in set_qam()
5521 	if (status < 0)  in set_qam()
5525 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);  in set_qam()
5526 	if (status < 0)  in set_qam()
5528 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);  in set_qam()
5529 	if (status < 0)  in set_qam()
5533 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);  in set_qam()
5534 	if (status < 0)  in set_qam()
5536 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);  in set_qam()
5537 	if (status < 0)  in set_qam()
5539 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);  in set_qam()
5540 	if (status < 0)  in set_qam()
5542 	status = write16(state, QAM_LC_MODE__A, 7);  in set_qam()
5543 	if (status < 0)  in set_qam()
5546 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);  in set_qam()
5547 	if (status < 0)  in set_qam()
5549 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);  in set_qam()
5550 	if (status < 0)  in set_qam()
5552 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);  in set_qam()
5553 	if (status < 0)  in set_qam()
5555 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);  in set_qam()
5556 	if (status < 0)  in set_qam()
5558 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);  in set_qam()
5559 	if (status < 0)  in set_qam()
5561 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);  in set_qam()
5562 	if (status < 0)  in set_qam()
5564 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);  in set_qam()
5565 	if (status < 0)  in set_qam()
5567 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);  in set_qam()
5568 	if (status < 0)  in set_qam()
5570 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);  in set_qam()
5571 	if (status < 0)  in set_qam()
5573 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);  in set_qam()
5574 	if (status < 0)  in set_qam()
5576 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);  in set_qam()
5577 	if (status < 0)  in set_qam()
5579 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);  in set_qam()
5580 	if (status < 0)  in set_qam()
5582 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);  in set_qam()
5583 	if (status < 0)  in set_qam()
5585 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);  in set_qam()
5586 	if (status < 0)  in set_qam()
5588 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);  in set_qam()
5589 	if (status < 0)  in set_qam()
5593 	status = write16(state, QAM_SY_SP_INV__A,  in set_qam()
5595 	if (status < 0)  in set_qam()
5599 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam()
5600 	if (status < 0)  in set_qam()
5606 		status = set_qam16(state);  in set_qam()
5609 		status = set_qam32(state);  in set_qam()
5613 		status = set_qam64(state);  in set_qam()
5616 		status = set_qam128(state);  in set_qam()
5619 		status = set_qam256(state);  in set_qam()
5622 		status = -EINVAL;  in set_qam()
5625 	if (status < 0)  in set_qam()
5629 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam()
5630 	if (status < 0)  in set_qam()
5636 	status = mpegts_dto_setup(state, state->m_operation_mode);  in set_qam()
5637 	if (status < 0)  in set_qam()
5641 	status = mpegts_start(state);  in set_qam()
5642 	if (status < 0)  in set_qam()
5644 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in set_qam()
5645 	if (status < 0)  in set_qam()
5647 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);  in set_qam()
5648 	if (status < 0)  in set_qam()
5650 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_qam()
5651 	if (status < 0)  in set_qam()
5655 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in set_qam()
5658 	if (status < 0)  in set_qam()
5665 	if (status < 0)  in set_qam()
5666 		pr_err("Error %d on %s\n", status, __func__);  in set_qam()
5667 	return status;  in set_qam()
5673 	int status;  in set_qam_standard()  local
5686 	status = power_up_qam(state);  in set_qam_standard()
5687 	if (status < 0)  in set_qam_standard()
5690 	status = qam_reset_qam(state);  in set_qam_standard()
5691 	if (status < 0)  in set_qam_standard()
5696 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_qam_standard()
5697 	if (status < 0)  in set_qam_standard()
5699 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_qam_standard()
5700 	if (status < 0)  in set_qam_standard()
5707 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,  in set_qam_standard()
5712 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,  in set_qam_standard()
5716 		if (status < 0)  in set_qam_standard()
5718 		status = bl_direct_cmd(state,  in set_qam_standard()
5725 		status = -EINVAL;  in set_qam_standard()
5727 	if (status < 0)  in set_qam_standard()
5730 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);  in set_qam_standard()
5731 	if (status < 0)  in set_qam_standard()
5733 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);  in set_qam_standard()
5734 	if (status < 0)  in set_qam_standard()
5736 	status = write16(state, IQM_CF_MIDTAP__A,  in set_qam_standard()
5738 	if (status < 0)  in set_qam_standard()
5741 	status = write16(state, IQM_RC_STRETCH__A, 21);  in set_qam_standard()
5742 	if (status < 0)  in set_qam_standard()
5744 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_qam_standard()
5745 	if (status < 0)  in set_qam_standard()
5747 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_qam_standard()
5748 	if (status < 0)  in set_qam_standard()
5750 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_qam_standard()
5751 	if (status < 0)  in set_qam_standard()
5753 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);  in set_qam_standard()
5754 	if (status < 0)  in set_qam_standard()
5757 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);  in set_qam_standard()
5758 	if (status < 0)  in set_qam_standard()
5760 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);  in set_qam_standard()
5761 	if (status < 0)  in set_qam_standard()
5763 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);  in set_qam_standard()
5764 	if (status < 0)  in set_qam_standard()
5766 	status = write16(state, IQM_AF_UPD_SEL__A, 0);  in set_qam_standard()
5767 	if (status < 0)  in set_qam_standard()
5771 	status = write16(state, IQM_CF_CLP_VAL__A, 500);  in set_qam_standard()
5772 	if (status < 0)  in set_qam_standard()
5774 	status = write16(state, IQM_CF_DATATH__A, 1000);  in set_qam_standard()
5775 	if (status < 0)  in set_qam_standard()
5777 	status = write16(state, IQM_CF_BYPASSDET__A, 1);  in set_qam_standard()
5778 	if (status < 0)  in set_qam_standard()
5780 	status = write16(state, IQM_CF_DET_LCT__A, 0);  in set_qam_standard()
5781 	if (status < 0)  in set_qam_standard()
5783 	status = write16(state, IQM_CF_WND_LEN__A, 1);  in set_qam_standard()
5784 	if (status < 0)  in set_qam_standard()
5786 	status = write16(state, IQM_CF_PKDTH__A, 1);  in set_qam_standard()
5787 	if (status < 0)  in set_qam_standard()
5789 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);  in set_qam_standard()
5790 	if (status < 0)  in set_qam_standard()
5794 	status = set_iqm_af(state, true);  in set_qam_standard()
5795 	if (status < 0)  in set_qam_standard()
5797 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);  in set_qam_standard()
5798 	if (status < 0)  in set_qam_standard()
5802 	status = adc_synchronization(state);  in set_qam_standard()
5803 	if (status < 0)  in set_qam_standard()
5807 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);  in set_qam_standard()
5808 	if (status < 0)  in set_qam_standard()
5812 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam_standard()
5813 	if (status < 0)  in set_qam_standard()
5819 	status = init_agc(state, true);  in set_qam_standard()
5820 	if (status < 0)  in set_qam_standard()
5822 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));  in set_qam_standard()
5823 	if (status < 0)  in set_qam_standard()
5827 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);  in set_qam_standard()
5828 	if (status < 0)  in set_qam_standard()
5830 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);  in set_qam_standard()
5831 	if (status < 0)  in set_qam_standard()
5835 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam_standard()
5837 	if (status < 0)  in set_qam_standard()
5838 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_standard()
5839 	return status;  in set_qam_standard()
5844 	int status;  in write_gpio()  local
5849 	status = write16(state, SCU_RAM_GPIO__A,  in write_gpio()
5851 	if (status < 0)  in write_gpio()
5855 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in write_gpio()
5856 	if (status < 0)  in write_gpio()
5862 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,  in write_gpio()
5864 			if (status < 0)  in write_gpio()
5868 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5869 			if (status < 0)  in write_gpio()
5876 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5877 			if (status < 0)  in write_gpio()
5882 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,  in write_gpio()
5884 			if (status < 0)  in write_gpio()
5888 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5889 			if (status < 0)  in write_gpio()
5896 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5897 			if (status < 0)  in write_gpio()
5902 			status = write16(state, SIO_PDR_GPIO_CFG__A,  in write_gpio()
5904 			if (status < 0)  in write_gpio()
5908 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5909 			if (status < 0)  in write_gpio()
5916 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5917 			if (status < 0)  in write_gpio()
5922 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in write_gpio()
5924 	if (status < 0)  in write_gpio()
5925 		pr_err("Error %d on %s\n", status, __func__);  in write_gpio()
5926 	return status;  in write_gpio()
5931 	int status = 0;  in switch_antenna_to_qam()  local
5947 		status = write_gpio(state);  in switch_antenna_to_qam()
5949 	if (status < 0)  in switch_antenna_to_qam()
5950 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_qam()
5951 	return status;  in switch_antenna_to_qam()
5956 	int status = 0;  in switch_antenna_to_dvbt()  local
5972 		status = write_gpio(state);  in switch_antenna_to_dvbt()
5974 	if (status < 0)  in switch_antenna_to_dvbt()
5975 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_dvbt()
5976 	return status;  in switch_antenna_to_dvbt()
5988 	int status;  in power_down_device()  local
5993 		status = ConfigureI2CBridge(state, true);  in power_down_device()
5994 		if (status < 0)  in power_down_device()
5998 	status = dvbt_enable_ofdm_token_ring(state, false);  in power_down_device()
5999 	if (status < 0)  in power_down_device()
6002 	status = write16(state, SIO_CC_PWD_MODE__A,  in power_down_device()
6004 	if (status < 0)  in power_down_device()
6006 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_down_device()
6007 	if (status < 0)  in power_down_device()
6010 	status = hi_cfg_command(state);  in power_down_device()
6012 	if (status < 0)  in power_down_device()
6013 		pr_err("Error %d on %s\n", status, __func__);  in power_down_device()
6015 	return status;  in power_down_device()
6020 	int status = 0, n = 0;  in init_drxk()  local
6027 		status = power_up_device(state);  in init_drxk()
6028 		if (status < 0)  in init_drxk()
6030 		status = drxx_open(state);  in init_drxk()
6031 		if (status < 0)  in init_drxk()
6034 		status = write16(state, SIO_CC_SOFT_RST__A,  in init_drxk()
6038 		if (status < 0)  in init_drxk()
6040 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in init_drxk()
6041 		if (status < 0)  in init_drxk()
6049 		status = get_device_capabilities(state);  in init_drxk()
6050 		if (status < 0)  in init_drxk()
6070 		status = init_hi(state);  in init_drxk()
6071 		if (status < 0)  in init_drxk()
6079 			status = write16(state, SCU_RAM_GPIO__A,  in init_drxk()
6081 			if (status < 0)  in init_drxk()
6086 		status = mpegts_disable(state);  in init_drxk()
6087 		if (status < 0)  in init_drxk()
6091 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);  in init_drxk()
6092 		if (status < 0)  in init_drxk()
6094 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);  in init_drxk()
6095 		if (status < 0)  in init_drxk()
6099 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6101 		if (status < 0)  in init_drxk()
6105 		status = write16(state, SIO_BL_COMM_EXEC__A,  in init_drxk()
6107 		if (status < 0)  in init_drxk()
6109 		status = bl_chain_cmd(state, 0, 6, 100);  in init_drxk()
6110 		if (status < 0)  in init_drxk()
6114 			status = download_microcode(state, state->fw->data,  in init_drxk()
6116 			if (status < 0)  in init_drxk()
6121 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6123 		if (status < 0)  in init_drxk()
6127 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in init_drxk()
6128 		if (status < 0)  in init_drxk()
6130 		status = drxx_open(state);  in init_drxk()
6131 		if (status < 0)  in init_drxk()
6137 		status = ctrl_power_mode(state, &power_mode);  in init_drxk()
6138 		if (status < 0)  in init_drxk()
6152 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,  in init_drxk()
6154 		if (status < 0)  in init_drxk()
6161 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,  in init_drxk()
6163 		if (status < 0)  in init_drxk()
6181 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);  in init_drxk()
6182 		if (status < 0)  in init_drxk()
6187 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);  in init_drxk()
6188 		if (status < 0)  in init_drxk()
6191 		status = mpegts_dto_init(state);  in init_drxk()
6192 		if (status < 0)  in init_drxk()
6194 		status = mpegts_stop(state);  in init_drxk()
6195 		if (status < 0)  in init_drxk()
6197 		status = mpegts_configure_polarity(state);  in init_drxk()
6198 		if (status < 0)  in init_drxk()
6200 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);  in init_drxk()
6201 		if (status < 0)  in init_drxk()
6204 		status = write_gpio(state);  in init_drxk()
6205 		if (status < 0)  in init_drxk()
6211 			status = power_down_device(state);  in init_drxk()
6212 			if (status < 0)  in init_drxk()
6234 	if (status < 0) {  in init_drxk()
6237 		pr_err("Error %d on %s\n", status, __func__);  in init_drxk()
6240 	return status;  in init_drxk()
6383 	int status;  in get_strength()  local
6409 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);  in get_strength()
6410 		if (status < 0)  in get_strength()
6411 			return status;  in get_strength()
6414 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);  in get_strength()
6415 		if (status < 0)  in get_strength()
6416 			return status;  in get_strength()
6442 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,  in get_strength()
6444 		if (status < 0)  in get_strength()
6445 			return status;  in get_strength()
6447 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,  in get_strength()
6449 		if (status < 0)  in get_strength()
6450 			return status;  in get_strength()
6486 	int status;  in drxk_get_stats()  local
6503 	/* get status */  in drxk_get_stats()
6549 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);  in drxk_get_stats()
6550 	if (status < 0)  in drxk_get_stats()
6554 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);  in drxk_get_stats()
6555 	if (status < 0)  in drxk_get_stats()
6560 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);  in drxk_get_stats()
6561 	if (status < 0)  in drxk_get_stats()
6565 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);  in drxk_get_stats()
6566 	if (status < 0)  in drxk_get_stats()
6570 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);  in drxk_get_stats()
6571 	if (status < 0)  in drxk_get_stats()
6575 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);  in drxk_get_stats()
6576 	if (status < 0)  in drxk_get_stats()
6602 	return status;  in drxk_get_stats()
6606 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)  in drxk_read_status()  argument
6617 	*status = state->fe_status;  in drxk_read_status()
6742 	int status;  in drxk_attach()  local
6799 		status = request_firmware(&fw, state->microcode_name,  in drxk_attach()
6801 		if (status < 0)  in drxk_attach()