Lines Matching +full:0 +full:x29
30 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
32 #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0)
33 #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0)
41 } while (0)
79 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
80 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
81 .FILTune = 0x27f /* 0.41 V */
86 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
87 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
88 .FILTune = 0x317 /* 0.90 V */
93 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
94 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
95 .FILTune = 0x145 /* 2.70 V */
116 .progdata = (0 << 19) | (0 << 9) | 0x40,
124 .progdata = (0 << 19) | (0 << 9) | 0x80,
132 .progdata = (0 << 19) | (1 << 9) | 0x01,
140 .progdata = (0 << 19) | (1 << 9) | 0x02,
148 .progdata = (0 << 19) | (1 << 9) | 0x04,
156 .progdata = (0 << 19) | (1 << 9) | 0x08,
164 .progdata = (0 << 19) | (1 << 9) | 0x10,
172 .progdata = (0 << 19) | (1 << 9) | 0x20,
180 .progdata = (0 << 19) | (1 << 9) | 0x40,
189 {0x00, 0x03}, /* Reset system */
190 {0x00, 0x00}, /* Clear reset */
191 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
192 {0x04, 0x10}, /* MPEG */
193 {0x05, 0x04}, /* MPEG */
194 {0x06, 0x31}, /* MPEG (default) */
195 {0x0b, 0x00}, /* Freq search start point (default) */
196 {0x0c, 0x00}, /* Demodulator sample gain (default) */
197 {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
198 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
199 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
200 {0x10, 0x01}, /* Default search inversion, no repeat (default) */
201 {0x16, 0x00}, /* Enable reading of frequency */
202 {0x17, 0x01}, /* Enable EsNO Ready Counter */
203 {0x1c, 0x80}, /* Enable error counter */
204 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
205 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
206 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
207 {0x29, 0x00}, /* DiSEqC LNB_DC off */
208 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
209 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
210 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
211 {0x2d, 0x00},
212 {0x2e, 0x00},
213 {0x2f, 0x00},
214 {0x30, 0x00},
215 {0x31, 0x00},
216 {0x32, 0x8c}, /* DiSEqC Parameters (default) */
217 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
218 {0x34, 0x00},
219 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
220 {0x36, 0x02}, /* DiSEqC Parameters (default) */
221 {0x37, 0x3a}, /* DiSEqC Parameters (default) */
222 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
223 {0x44, 0x00}, /* Constellation (default) */
224 {0x45, 0x00}, /* Symbol count (default) */
225 {0x46, 0x0d}, /* Symbol rate estimator on (default) */
226 {0x56, 0xc1}, /* Error Counter = Viterbi BER */
227 {0x57, 0xff}, /* Error Counter Window (default) */
228 {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
229 {0x67, 0x83}, /* Non-DCII symbol clock */
237 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 in cx24123_i2c_writereg()
245 printk("%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n", in cx24123_i2c_writereg()
250 return 0; in cx24123_i2c_writereg()
256 u8 b = 0; in cx24123_i2c_readreg()
258 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, in cx24123_i2c_readreg()
265 err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); in cx24123_i2c_readreg()
282 u8 nom_reg = cx24123_readreg(state, 0x0e); in cx24123_set_inversion()
283 u8 auto_reg = cx24123_readreg(state, 0x10); in cx24123_set_inversion()
288 cx24123_writereg(state, 0x0e, nom_reg & ~0x80); in cx24123_set_inversion()
289 cx24123_writereg(state, 0x10, auto_reg | 0x80); in cx24123_set_inversion()
293 cx24123_writereg(state, 0x0e, nom_reg | 0x80); in cx24123_set_inversion()
294 cx24123_writereg(state, 0x10, auto_reg | 0x80); in cx24123_set_inversion()
298 cx24123_writereg(state, 0x10, auto_reg & ~0x80); in cx24123_set_inversion()
304 return 0; in cx24123_set_inversion()
312 val = cx24123_readreg(state, 0x1b) >> 7; in cx24123_get_inversion()
314 if (val == 0) { in cx24123_get_inversion()
322 return 0; in cx24123_get_inversion()
327 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; in cx24123_set_fec()
334 cx24123_writereg(state, 0x43, in cx24123_set_fec()
335 cx24123_readreg(state, 0x43) | 0x01); in cx24123_set_fec()
337 cx24123_writereg(state, 0x43, in cx24123_set_fec()
338 cx24123_readreg(state, 0x43) & ~0x01); in cx24123_set_fec()
343 cx24123_writereg(state, 0x0e, nom_reg | 0x01); in cx24123_set_fec()
344 cx24123_writereg(state, 0x0f, 0x02); in cx24123_set_fec()
348 cx24123_writereg(state, 0x0e, nom_reg | 0x02); in cx24123_set_fec()
349 cx24123_writereg(state, 0x0f, 0x04); in cx24123_set_fec()
353 cx24123_writereg(state, 0x0e, nom_reg | 0x03); in cx24123_set_fec()
354 cx24123_writereg(state, 0x0f, 0x08); in cx24123_set_fec()
358 cx24123_writereg(state, 0x0e, nom_reg | 0x04); in cx24123_set_fec()
359 cx24123_writereg(state, 0x0f, 0x10); in cx24123_set_fec()
363 cx24123_writereg(state, 0x0e, nom_reg | 0x05); in cx24123_set_fec()
364 cx24123_writereg(state, 0x0f, 0x20); in cx24123_set_fec()
368 cx24123_writereg(state, 0x0e, nom_reg | 0x06); in cx24123_set_fec()
369 cx24123_writereg(state, 0x0f, 0x40); in cx24123_set_fec()
373 cx24123_writereg(state, 0x0e, nom_reg | 0x07); in cx24123_set_fec()
374 cx24123_writereg(state, 0x0f, 0x80); in cx24123_set_fec()
378 cx24123_writereg(state, 0x0f, 0xfe); in cx24123_set_fec()
384 return 0; in cx24123_set_fec()
391 ret = cx24123_readreg(state, 0x1b); in cx24123_get_fec()
392 if (ret < 0) in cx24123_get_fec()
394 ret = ret & 0x07; in cx24123_get_fec()
423 return 0; in cx24123_get_fec()
430 u32 exp, nearest = 0; in cx24123_int_log2()
474 /* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */ in cx24123_set_symbolrate()
480 cx24123_writereg(state, 0x01, pll_mult * 6); in cx24123_set_symbolrate()
482 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f); in cx24123_set_symbolrate()
483 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff); in cx24123_set_symbolrate()
484 cx24123_writereg(state, 0x0a, ratio & 0xff); in cx24123_set_symbolrate()
488 tmp = cx24123_readreg(state, 0x0c) & ~0xe0; in cx24123_set_symbolrate()
489 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); in cx24123_set_symbolrate()
491 dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", in cx24123_set_symbolrate()
494 return 0; in cx24123_set_symbolrate()
506 u32 ndiv = 0, adiv = 0, vco_div = 0; in cx24123_pll_calculate()
507 int i = 0; in cx24123_pll_calculate()
509 int band = 0; in cx24123_pll_calculate()
515 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; in cx24123_pll_calculate()
516 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; in cx24123_pll_calculate()
517 state->bandselectarg = cx24123_bandselect_vals[0].progdata; in cx24123_pll_calculate()
518 vco_div = cx24123_bandselect_vals[0].VCOdivider; in cx24123_pll_calculate()
522 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) { in cx24123_pll_calculate()
534 for (i = 0; i < num_bands; i++) { in cx24123_pll_calculate()
549 pump = 0x01; in cx24123_pll_calculate()
551 pump = 0x02; in cx24123_pll_calculate()
557 (2 * XTAL / 1000)) / 32) & 0x1ff; in cx24123_pll_calculate()
559 (2 * XTAL / 1000)) % 32) & 0x1f; in cx24123_pll_calculate()
561 if (adiv == 0 && ndiv > 0) in cx24123_pll_calculate()
569 return 0; in cx24123_pll_calculate()
582 dprintk("pll writereg called, data=0x%08x\n", data); in cx24123_pll_writereg()
587 /* Reset the demod pll word length to 0x15 bits */ in cx24123_pll_writereg()
588 cx24123_writereg(state, 0x21, 0x15); in cx24123_pll_writereg()
592 cx24123_writereg(state, 0x22, (data >> 16) & 0xff); in cx24123_pll_writereg()
593 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { in cx24123_pll_writereg()
604 cx24123_writereg(state, 0x22, (data >> 8) & 0xff); in cx24123_pll_writereg()
605 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { in cx24123_pll_writereg()
617 cx24123_writereg(state, 0x22, (data) & 0xff); in cx24123_pll_writereg()
618 while ((cx24123_readreg(state, 0x20) & 0x80)) { in cx24123_pll_writereg()
628 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); in cx24123_pll_writereg()
629 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); in cx24123_pll_writereg()
631 return 0; in cx24123_pll_writereg()
642 if (cx24123_pll_calculate(fe) != 0) { in cx24123_pll_tune()
656 val = cx24123_readreg(state, 0x28) & ~0x3; in cx24123_pll_tune()
657 cx24123_writereg(state, 0x27, state->FILTune >> 2); in cx24123_pll_tune()
658 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); in cx24123_pll_tune()
663 return 0; in cx24123_pll_tune()
668 * 0x23:
672 * [0:0] = BTI start
675 /* mode == 1 -> i2c-repeater, 0 -> bti */
678 u8 r = cx24123_readreg(state, 0x23) & 0x1e; in cx24123_repeater_mode()
683 return cx24123_writereg(state, 0x23, r); in cx24123_repeater_mode()
694 for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) in cx24123_initfe()
700 cx24123_writereg(state, 0x32, in cx24123_initfe()
701 cx24123_readreg(state, 0x32) | 0x02); in cx24123_initfe()
704 cx24123_repeater_mode(state, 1, 0); in cx24123_initfe()
706 return 0; in cx24123_initfe()
715 val = cx24123_readreg(state, 0x29) & ~0x40; in cx24123_set_voltage()
720 return cx24123_writereg(state, 0x29, val & 0x7f); in cx24123_set_voltage()
723 return cx24123_writereg(state, 0x29, val | 0x80); in cx24123_set_voltage()
726 return 0; in cx24123_set_voltage()
731 return 0; in cx24123_set_voltage()
738 while (!(cx24123_readreg(state, 0x29) & 0x40)) { in cx24123_wait_for_diseqc()
757 tone = cx24123_readreg(state, 0x29); in cx24123_send_diseqc_msg()
758 if (tone & 0x10) in cx24123_send_diseqc_msg()
759 cx24123_writereg(state, 0x29, tone & ~0x50); in cx24123_send_diseqc_msg()
765 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); in cx24123_send_diseqc_msg()
767 for (i = 0; i < cmd->msg_len; i++) in cx24123_send_diseqc_msg()
768 cx24123_writereg(state, 0x2C + i, cmd->msg[i]); in cx24123_send_diseqc_msg()
770 val = cx24123_readreg(state, 0x29); in cx24123_send_diseqc_msg()
771 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | in cx24123_send_diseqc_msg()
778 if (tone & 0x10) in cx24123_send_diseqc_msg()
779 cx24123_writereg(state, 0x29, tone & ~0x40); in cx24123_send_diseqc_msg()
781 return 0; in cx24123_send_diseqc_msg()
793 tone = cx24123_readreg(state, 0x29); in cx24123_diseqc_send_burst()
794 if (tone & 0x10) in cx24123_diseqc_send_burst()
795 cx24123_writereg(state, 0x29, tone & ~0x50); in cx24123_diseqc_send_burst()
801 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); in cx24123_diseqc_send_burst()
803 val = cx24123_readreg(state, 0x29); in cx24123_diseqc_send_burst()
805 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); in cx24123_diseqc_send_burst()
807 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); in cx24123_diseqc_send_burst()
812 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); in cx24123_diseqc_send_burst()
815 if (tone & 0x10) in cx24123_diseqc_send_burst()
816 cx24123_writereg(state, 0x29, tone & ~0x40); in cx24123_diseqc_send_burst()
818 return 0; in cx24123_diseqc_send_burst()
824 int sync = cx24123_readreg(state, 0x14); in cx24123_read_status()
826 *status = 0; in cx24123_read_status()
828 u32 tun_status = 0; in cx24123_read_status()
834 int lock = cx24123_readreg(state, 0x20); in cx24123_read_status()
835 if (lock & 0x01) in cx24123_read_status()
839 if (sync & 0x02) in cx24123_read_status()
841 if (sync & 0x04) in cx24123_read_status()
845 if (sync & 0x08) in cx24123_read_status()
847 if (sync & 0x80) in cx24123_read_status()
850 return 0; in cx24123_read_status()
864 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | in cx24123_read_ber()
865 (cx24123_readreg(state, 0x1d) << 8 | in cx24123_read_ber()
866 cx24123_readreg(state, 0x1e)); in cx24123_read_ber()
870 return 0; in cx24123_read_ber()
879 *signal_strength = cx24123_readreg(state, 0x3b) << 8; in cx24123_read_signal_strength()
883 return 0; in cx24123_read_signal_strength()
892 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | in cx24123_read_snr()
893 (u16)cx24123_readreg(state, 0x19)); in cx24123_read_snr()
897 return 0; in cx24123_read_snr()
908 state->config->set_ts_params(fe, 0); in cx24123_set_frontend()
925 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); in cx24123_set_frontend()
926 cx24123_writereg(state, 0x00, 0x10); in cx24123_set_frontend()
927 cx24123_writereg(state, 0x00, 0); in cx24123_set_frontend()
932 return 0; in cx24123_set_frontend()
942 if (cx24123_get_inversion(state, &p->inversion) != 0) { in cx24123_get_frontend()
946 if (cx24123_get_fec(state, &p->fec_inner) != 0) { in cx24123_get_frontend()
953 return 0; in cx24123_get_frontend()
964 val = cx24123_readreg(state, 0x29) & ~0x40; in cx24123_set_tone()
969 return cx24123_writereg(state, 0x29, val | 0x10); in cx24123_set_tone()
972 return cx24123_writereg(state, 0x29, val & 0xef); in cx24123_set_tone()
978 return 0; in cx24123_set_tone()
987 int retval = 0; in cx24123_tune()
1059 state->demod_rev = cx24123_readreg(state, 0x00); in cx24123_attach()
1061 case 0xe1: in cx24123_attach()
1064 case 0xd1: in cx24123_attach()
1079 cx24123_repeater_mode(state, 1, 0); in cx24123_attach()
1087 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { in cx24123_attach()