1 // SPDX-License-Identifier: GPL-2.0
23 /* TX0/RX0/RXDB[0-3] */
34 /* Please not change TX & RX */
36 	IMX_MU_TYPE_TX		= 0, /* Tx */
38 	IMX_MU_TYPE_TXDB	= 2, /* Tx doorbell */
84 	struct mbox_controller	mbox;  member
106 	int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);  member
117 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
118 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
119 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
122 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
124 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
126 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
128 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
134 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)  in to_imx_mu_priv()  argument
136 	return container_of(mbox, struct imx_mu_priv, mbox);  in to_imx_mu_priv()
141 	iowrite32(val, priv->base + offs);  in imx_mu_write()
146 	return ioread32(priv->base + offs);  in imx_mu_read()
155 	dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);  in imx_mu_tx_waiting_write()
158 		status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);  in imx_mu_tx_waiting_write()
159 		can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);  in imx_mu_tx_waiting_write()
163 		dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",  in imx_mu_tx_waiting_write()
165 		return -ETIME;  in imx_mu_tx_waiting_write()
168 	imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);  in imx_mu_tx_waiting_write()
179 	dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);  in imx_mu_rx_waiting_read()
182 		status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);  in imx_mu_rx_waiting_read()
183 		can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);  in imx_mu_rx_waiting_read()
187 		dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",  in imx_mu_rx_waiting_read()
189 		return -ETIME;  in imx_mu_rx_waiting_read()
192 	*val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);  in imx_mu_rx_waiting_read()
193 	dev_dbg(priv->dev, "Read %.8x\n", *val);  in imx_mu_rx_waiting_read()
203 	spin_lock_irqsave(&priv->xcr_lock, flags);  in imx_mu_xcr_rmw()
204 	val = imx_mu_read(priv, priv->dcfg->xCR[type]);  in imx_mu_xcr_rmw()
207 	imx_mu_write(priv, val, priv->dcfg->xCR[type]);  in imx_mu_xcr_rmw()
208 	spin_unlock_irqrestore(&priv->xcr_lock, flags);  in imx_mu_xcr_rmw()
219 	switch (cp->type) {  in imx_mu_generic_tx()
221 		imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);  in imx_mu_generic_tx()
222 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_generic_tx()
225 		imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);  in imx_mu_generic_tx()
226 		tasklet_schedule(&cp->txdb_tasklet);  in imx_mu_generic_tx()
229 		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);  in imx_mu_generic_tx()
230 		return -EINVAL;  in imx_mu_generic_tx()
241 	dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);  in imx_mu_generic_rx()
242 	mbox_chan_received_data(cp->chan, (void *)&dat);  in imx_mu_generic_rx()
250 	imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),  in imx_mu_generic_rxdb()
251 		     priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_generic_rxdb()
252 	mbox_chan_received_data(cp->chan, NULL);  in imx_mu_generic_rxdb()
264 	if (priv->dcfg->type & IMX_MU_V2_S4) {  in imx_mu_specific_tx()
265 		size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;  in imx_mu_specific_tx()
269 		size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;  in imx_mu_specific_tx()
274 	switch (cp->type) {  in imx_mu_specific_tx()
277 		 * msg->hdr.size specifies the number of u32 words while  in imx_mu_specific_tx()
286 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, si…  in imx_mu_specific_tx()
287 			return -EINVAL;  in imx_mu_specific_tx()
291 			imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);  in imx_mu_specific_tx()
293 			ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],  in imx_mu_specific_tx()
295 						 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),  in imx_mu_specific_tx()
298 				dev_err(priv->dev, "Send data index: %d timeout\n", i);  in imx_mu_specific_tx()
301 			imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);  in imx_mu_specific_tx()
304 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_specific_tx()
307 		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);  in imx_mu_specific_tx()
308 		return -EINVAL;  in imx_mu_specific_tx()
321 	data = (u32 *)priv->msg;  in imx_mu_specific_rx()
323 	imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));  in imx_mu_specific_rx()
324 	*data++ = imx_mu_read(priv, priv->dcfg->xRR);  in imx_mu_specific_rx()
326 	if (priv->dcfg->type & IMX_MU_V2_S4) {  in imx_mu_specific_rx()
327 		size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;  in imx_mu_specific_rx()
330 		size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;  in imx_mu_specific_rx()
335 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, si…  in imx_mu_specific_rx()
336 		return -EINVAL;  in imx_mu_specific_rx()
340 		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,  in imx_mu_specific_rx()
341 					 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,  in imx_mu_specific_rx()
344 			dev_err(priv->dev, "timeout read idx %d\n", i);  in imx_mu_specific_rx()
347 		*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);  in imx_mu_specific_rx()
350 	imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);  in imx_mu_specific_rx()
351 	mbox_chan_received_data(cp->chan, (void *)priv->msg);  in imx_mu_specific_rx()
365 	dev_dbg(priv->dev, "Sending message\n");  in imx_mu_seco_tx()
367 	switch (cp->type) {  in imx_mu_seco_tx()
369 		byte_size = msg->hdr.size * sizeof(u32);  in imx_mu_seco_tx()
375 			dev_err(priv->dev,  in imx_mu_seco_tx()
376 				"Exceed max msg size (%zu) on TX, got: %i\n",  in imx_mu_seco_tx()
378 			return -EINVAL;  in imx_mu_seco_tx()
385 		dev_dbg(priv->dev, "Sending header\n");  in imx_mu_seco_tx()
386 		imx_mu_write(priv, *arg++, priv->dcfg->xTR);  in imx_mu_seco_tx()
389 		dev_dbg(priv->dev, "Sending signaling\n");  in imx_mu_seco_tx()
391 			       IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);  in imx_mu_seco_tx()
394 		for (i = 1; i < 4 && i < msg->hdr.size; i++) {  in imx_mu_seco_tx()
395 			dev_dbg(priv->dev, "Sending word %d\n", i);  in imx_mu_seco_tx()
397 				     priv->dcfg->xTR + (i % 4) * 4);  in imx_mu_seco_tx()
401 		for (; i < msg->hdr.size; i++) {  in imx_mu_seco_tx()
402 			dev_dbg(priv->dev, "Sending word %d\n", i);  in imx_mu_seco_tx()
405 				dev_err(priv->dev, "Timeout tx %d\n", i);  in imx_mu_seco_tx()
410 		/* Simulate hack for mbox framework */  in imx_mu_seco_tx()
411 		tasklet_schedule(&cp->txdb_tasklet);  in imx_mu_seco_tx()
415 		dev_warn_ratelimited(priv->dev,  in imx_mu_seco_tx()
417 				     cp->type);  in imx_mu_seco_tx()
418 		return -EINVAL;  in imx_mu_seco_tx()
432 	dev_dbg(priv->dev, "Receiving message\n");  in imx_mu_seco_rxdb()
435 	dev_dbg(priv->dev, "Receiving header\n");  in imx_mu_seco_rxdb()
436 	*data++ = imx_mu_read(priv, priv->dcfg->xRR);  in imx_mu_seco_rxdb()
439 		dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",  in imx_mu_seco_rxdb()
441 		err = -EINVAL;  in imx_mu_seco_rxdb()
447 		dev_dbg(priv->dev, "Receiving word %d\n", i);  in imx_mu_seco_rxdb()
450 			dev_err(priv->dev, "Timeout rx %d\n", i);  in imx_mu_seco_rxdb()
456 	imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),  in imx_mu_seco_rxdb()
457 		     priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_seco_rxdb()
463 	dev_dbg(priv->dev, "Sending message to client\n");  in imx_mu_seco_rxdb()
464 	mbox_chan_received_data(cp->chan, (void *)&msg);  in imx_mu_seco_rxdb()
469 	mbox_chan_received_data(cp->chan, ERR_PTR(err));  in imx_mu_seco_rxdb()
479 	mbox_chan_txdone(cp->chan, 0);  in imx_mu_txdb_tasklet()
485 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_isr()
486 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_isr()
489 	switch (cp->type) {  in imx_mu_isr()
491 		ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);  in imx_mu_isr()
492 		val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);  in imx_mu_isr()
493 		val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &  in imx_mu_isr()
494 			(ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
497 		ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);  in imx_mu_isr()
498 		val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);  in imx_mu_isr()
499 		val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &  in imx_mu_isr()
500 			(ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
503 		ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);  in imx_mu_isr()
504 		val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_isr()
505 		val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &  in imx_mu_isr()
506 			(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
511 		dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",  in imx_mu_isr()
512 				     cp->type);  in imx_mu_isr()
519 	if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&  in imx_mu_isr()
520 	    (cp->type == IMX_MU_TYPE_TX)) {  in imx_mu_isr()
521 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
523 	} else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&  in imx_mu_isr()
524 		   (cp->type == IMX_MU_TYPE_RX)) {  in imx_mu_isr()
525 		priv->dcfg->rx(priv, cp);  in imx_mu_isr()
526 	} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&  in imx_mu_isr()
527 		   (cp->type == IMX_MU_TYPE_RXDB)) {  in imx_mu_isr()
528 		priv->dcfg->rxdb(priv, cp);  in imx_mu_isr()
530 		dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");  in imx_mu_isr()
534 	if (priv->suspend)  in imx_mu_isr()
542 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_send_data()
543 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_send_data()
545 	return priv->dcfg->tx(priv, cp, data);  in imx_mu_send_data()
550 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_startup()
551 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_startup()
555 	pm_runtime_get_sync(priv->dev);  in imx_mu_startup()
556 	if (cp->type == IMX_MU_TYPE_TXDB) {  in imx_mu_startup()
557 		/* Tx doorbell don't have ACK support */  in imx_mu_startup()
558 		tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,  in imx_mu_startup()
564 	if (!priv->dev->pm_domain)  in imx_mu_startup()
567 	if (!(priv->dcfg->type & IMX_MU_V2_IRQ))  in imx_mu_startup()
570 	ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);  in imx_mu_startup()
572 		dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);  in imx_mu_startup()
576 	switch (cp->type) {  in imx_mu_startup()
578 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_startup()
581 		imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_startup()
592 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_shutdown()
593 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_shutdown()
597 	if (cp->type == IMX_MU_TYPE_TXDB) {  in imx_mu_shutdown()
598 		tasklet_kill(&cp->txdb_tasklet);  in imx_mu_shutdown()
599 		pm_runtime_put_sync(priv->dev);  in imx_mu_shutdown()
603 	switch (cp->type) {  in imx_mu_shutdown()
605 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));  in imx_mu_shutdown()
608 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));  in imx_mu_shutdown()
611 		imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));  in imx_mu_shutdown()
614 		imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);  in imx_mu_shutdown()
615 		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,  in imx_mu_shutdown()
616 					 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);  in imx_mu_shutdown()
618 			dev_warn(priv->dev, "RST channel timeout\n");  in imx_mu_shutdown()
624 	free_irq(priv->irq[cp->type], chan);  in imx_mu_shutdown()
625 	pm_runtime_put_sync(priv->dev);  in imx_mu_shutdown()
634 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,  in imx_mu_specific_xlate()  argument
639 	if (sp->args_count != 2) {  in imx_mu_specific_xlate()
640 		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);  in imx_mu_specific_xlate()
641 		return ERR_PTR(-EINVAL);  in imx_mu_specific_xlate()
644 	type = sp->args[0]; /* channel type */  in imx_mu_specific_xlate()
645 	idx = sp->args[1]; /* index */  in imx_mu_specific_xlate()
651 			dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);  in imx_mu_specific_xlate()
658 		dev_err(mbox->dev, "Invalid chan type: %d\n", type);  in imx_mu_specific_xlate()
659 		return ERR_PTR(-EINVAL);  in imx_mu_specific_xlate()
662 	if (chan >= mbox->num_chans) {  in imx_mu_specific_xlate()
663 		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);  in imx_mu_specific_xlate()
664 		return ERR_PTR(-EINVAL);  in imx_mu_specific_xlate()
667 	return &mbox->chans[chan];  in imx_mu_specific_xlate()
670 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,  in imx_mu_xlate()  argument
675 	if (sp->args_count != 2) {  in imx_mu_xlate()
676 		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);  in imx_mu_xlate()
677 		return ERR_PTR(-EINVAL);  in imx_mu_xlate()
680 	type = sp->args[0]; /* channel type */  in imx_mu_xlate()
681 	idx = sp->args[1]; /* index */  in imx_mu_xlate()
684 	if (chan >= mbox->num_chans) {  in imx_mu_xlate()
685 		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);  in imx_mu_xlate()
686 		return ERR_PTR(-EINVAL);  in imx_mu_xlate()
689 	return &mbox->chans[chan];  in imx_mu_xlate()
692 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,  in imx_mu_seco_xlate()  argument
697 	if (sp->args_count < 1) {  in imx_mu_seco_xlate()
698 		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);  in imx_mu_seco_xlate()
699 		return ERR_PTR(-EINVAL);  in imx_mu_seco_xlate()
702 	type = sp->args[0]; /* channel type */  in imx_mu_seco_xlate()
706 		dev_err(mbox->dev, "Invalid type: %d\n", type);  in imx_mu_seco_xlate()
707 		return ERR_PTR(-EINVAL);  in imx_mu_seco_xlate()
710 	return imx_mu_xlate(mbox, sp);  in imx_mu_seco_xlate()
719 		struct imx_mu_con_priv *cp = &priv->con_priv[i];  in imx_mu_init_generic()
721 		cp->idx = i % 4;  in imx_mu_init_generic()
722 		cp->type = i >> 2;  in imx_mu_init_generic()
723 		cp->chan = &priv->mbox_chans[i];  in imx_mu_init_generic()
724 		priv->mbox_chans[i].con_priv = cp;  in imx_mu_init_generic()
725 		snprintf(cp->irq_desc, sizeof(cp->irq_desc),  in imx_mu_init_generic()
726 			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);  in imx_mu_init_generic()
729 	priv->mbox.num_chans = IMX_MU_CHANS;  in imx_mu_init_generic()
730 	priv->mbox.of_xlate = imx_mu_xlate;  in imx_mu_init_generic()
732 	if (priv->side_b)  in imx_mu_init_generic()
737 		imx_mu_write(priv, 0, priv->dcfg->xCR[i]);  in imx_mu_init_generic()
740 	val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_init_generic()
741 	imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_init_generic()
745 		imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);  in imx_mu_init_generic()
751 	int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;  in imx_mu_init_specific()
754 		struct imx_mu_con_priv *cp = &priv->con_priv[i];  in imx_mu_init_specific()
756 		cp->idx = i < 2 ? 0 : i - 2;  in imx_mu_init_specific()
757 		cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;  in imx_mu_init_specific()
758 		cp->chan = &priv->mbox_chans[i];  in imx_mu_init_specific()
759 		priv->mbox_chans[i].con_priv = cp;  in imx_mu_init_specific()
760 		snprintf(cp->irq_desc, sizeof(cp->irq_desc),  in imx_mu_init_specific()
761 			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);  in imx_mu_init_specific()
764 	priv->mbox.num_chans = num_chans;  in imx_mu_init_specific()
765 	priv->mbox.of_xlate = imx_mu_specific_xlate;  in imx_mu_init_specific()
769 		imx_mu_write(priv, 0, priv->dcfg->xCR[i]);  in imx_mu_init_specific()
775 	priv->mbox.of_xlate = imx_mu_seco_xlate;  in imx_mu_init_seco()
780 	struct device *dev = &pdev->dev;  in imx_mu_probe()
781 	struct device_node *np = dev->of_node;  in imx_mu_probe()
789 		return -ENOMEM;  in imx_mu_probe()
791 	priv->dev = dev;  in imx_mu_probe()
793 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in imx_mu_probe()
794 	if (IS_ERR(priv->base))  in imx_mu_probe()
795 		return PTR_ERR(priv->base);  in imx_mu_probe()
799 		return -EINVAL;  in imx_mu_probe()
800 	priv->dcfg = dcfg;  in imx_mu_probe()
801 	if (priv->dcfg->type & IMX_MU_V2_IRQ) {  in imx_mu_probe()
802 		priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");  in imx_mu_probe()
803 		if (priv->irq[IMX_MU_TYPE_TX] < 0)  in imx_mu_probe()
804 			return priv->irq[IMX_MU_TYPE_TX];  in imx_mu_probe()
805 		priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");  in imx_mu_probe()
806 		if (priv->irq[IMX_MU_TYPE_RX] < 0)  in imx_mu_probe()
807 			return priv->irq[IMX_MU_TYPE_RX];  in imx_mu_probe()
814 			priv->irq[i] = ret;  in imx_mu_probe()
817 	if (priv->dcfg->type & IMX_MU_V2_S4)  in imx_mu_probe()
822 	priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);  in imx_mu_probe()
823 	if (!priv->msg)  in imx_mu_probe()
824 		return -ENOMEM;  in imx_mu_probe()
826 	priv->clk = devm_clk_get(dev, NULL);  in imx_mu_probe()
827 	if (IS_ERR(priv->clk)) {  in imx_mu_probe()
828 		if (PTR_ERR(priv->clk) != -ENOENT)  in imx_mu_probe()
829 			return PTR_ERR(priv->clk);  in imx_mu_probe()
831 		priv->clk = NULL;  in imx_mu_probe()
834 	ret = clk_prepare_enable(priv->clk);  in imx_mu_probe()
840 	priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");  in imx_mu_probe()
842 	priv->dcfg->init(priv);  in imx_mu_probe()
844 	spin_lock_init(&priv->xcr_lock);  in imx_mu_probe()
846 	priv->mbox.dev = dev;  in imx_mu_probe()
847 	priv->mbox.ops = &imx_mu_ops;  in imx_mu_probe()
848 	priv->mbox.chans = priv->mbox_chans;  in imx_mu_probe()
849 	priv->mbox.txdone_irq = true;  in imx_mu_probe()
853 	ret = devm_mbox_controller_register(dev, &priv->mbox);  in imx_mu_probe()
855 		clk_disable_unprepare(priv->clk);  in imx_mu_probe()
869 	clk_disable_unprepare(priv->clk);  in imx_mu_probe()
875 	clk_disable_unprepare(priv->clk);  in imx_mu_probe()
883 	pm_runtime_disable(priv->dev);  in imx_mu_remove()
889 	.tx	= imx_mu_generic_tx,
900 	.tx	= imx_mu_generic_tx,
911 	.tx	= imx_mu_generic_tx,
923 	.tx	= imx_mu_specific_tx,
934 	.tx	= imx_mu_specific_tx,
945 	.tx	= imx_mu_specific_tx,
956 	.tx	= imx_mu_seco_tx,
967 	{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
968 	{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
969 	{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
970 	{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
971 	{ .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
972 	{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
973 	{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
983 	if (!priv->clk) {  in imx_mu_suspend_noirq()
985 			priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);  in imx_mu_suspend_noirq()
988 	priv->suspend = true;  in imx_mu_suspend_noirq()
1006 	if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {  in imx_mu_resume_noirq()
1008 			imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);  in imx_mu_resume_noirq()
1011 	priv->suspend = false;  in imx_mu_resume_noirq()
1020 	clk_disable_unprepare(priv->clk);  in imx_mu_runtime_suspend()
1030 	ret = clk_prepare_enable(priv->clk);  in imx_mu_runtime_resume()