1 // SPDX-License-Identifier: GPL-2.0
36  * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
37  * PRIO is read-write 32-bit with 4-bits per IRQ (**)
38  * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
39  * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
40  * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
42  * (*) May be accessed by more than one driver instance - lock needed
43  * (**) Read-modify-write access by one driver instance - lock needed
44  * (***) Accessed by one driver instance only - no locking needed
51 	int width;  member
74 	int irlm_bit;		/* -1 if non-existent */
100 	struct intc_irqpin_iomem *i = &p->iomem[reg];  in intc_irqpin_read()
102 	return i->read(i->iomem);  in intc_irqpin_read()
108 	struct intc_irqpin_iomem *i = &p->iomem[reg];  in intc_irqpin_write()
110 	i->write(i->iomem, data);  in intc_irqpin_write()
116 	return BIT((p->iomem[reg].width - 1) - hw_irq);  in intc_irqpin_hwirq_mask()
129 					  int width, int value)  in intc_irqpin_read_modify_write()  argument
137 	tmp &= ~(((1 << width) - 1) << shift);  in intc_irqpin_read_modify_write()
147 	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */  in intc_irqpin_mask_unmask_prio()
149 	int shift = 32 - (irq + 1) * bitfield_width;  in intc_irqpin_mask_unmask_prio()
153 				      do_mask ? 0 : (1 << bitfield_width) - 1);  in intc_irqpin_mask_unmask_prio()
158 	/* The SENSE register is assumed to be 32-bit. */  in intc_irqpin_set_sense()
159 	int bitfield_width = p->sense_bitfield_width;  in intc_irqpin_set_sense()
160 	int shift = 32 - (irq + 1) * bitfield_width;  in intc_irqpin_set_sense()
162 	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);  in intc_irqpin_set_sense()
165 		return -EINVAL;  in intc_irqpin_set_sense()
174 	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",  in intc_irqpin_dbg()
175 		str, i->requested_irq, i->hw_irq, i->domain_irq);  in intc_irqpin_dbg()
183 	intc_irqpin_dbg(&p->irq[hw_irq], "enable");  in intc_irqpin_irq_enable()
192 	intc_irqpin_dbg(&p->irq[hw_irq], "disable");  in intc_irqpin_irq_disable()
201 	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");  in intc_irqpin_shared_irq_enable()
204 	p->shared_irq_mask &= ~BIT(hw_irq);  in intc_irqpin_shared_irq_enable()
212 	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");  in intc_irqpin_shared_irq_disable()
215 	p->shared_irq_mask |= BIT(hw_irq);  in intc_irqpin_shared_irq_disable()
221 	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;  in intc_irqpin_irq_enable_force()
226 	 * assumes non-shared interrupt with 1:1 mapping  in intc_irqpin_irq_enable_force()
229 	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));  in intc_irqpin_irq_enable_force()
235 	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;  in intc_irqpin_irq_disable_force()
238 	 * assumes non-shared interrupt with 1:1 mapping  in intc_irqpin_irq_disable_force()
241 	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));  in intc_irqpin_irq_disable_force()
262 		return -EINVAL;  in intc_irqpin_irq_set_type()
273 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);  in intc_irqpin_irq_set_wake()
275 		atomic_inc(&p->wakeup_path);  in intc_irqpin_irq_set_wake()
277 		atomic_dec(&p->wakeup_path);  in intc_irqpin_irq_set_wake()
285 	struct intc_irqpin_priv *p = i->p;  in intc_irqpin_irq_handler()
289 	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);  in intc_irqpin_irq_handler()
294 		generic_handle_irq(i->domain_irq);  in intc_irqpin_irq_handler()
308 		if (reg_source & BIT(7 - k)) {  in intc_irqpin_shared_irq_handler()
309 			if (BIT(k) & p->shared_irq_mask)  in intc_irqpin_shared_irq_handler()
312 			status |= intc_irqpin_irq_handler(irq, &p->irq[k]);  in intc_irqpin_shared_irq_handler()
331 	struct intc_irqpin_priv *p = h->host_data;  in intc_irqpin_irq_domain_map()
333 	p->irq[hw].domain_irq = virq;  in intc_irqpin_irq_domain_map()
334 	p->irq[hw].hw_irq = hw;  in intc_irqpin_irq_domain_map()
336 	intc_irqpin_dbg(&p->irq[hw], "map");  in intc_irqpin_irq_domain_map()
337 	irq_set_chip_data(virq, h->host_data);  in intc_irqpin_irq_domain_map()
340 	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);  in intc_irqpin_irq_domain_map()
354 	.irlm_bit = -1,
358 	{ .compatible = "renesas,intc-irqpin", },
359 	{ .compatible = "renesas,intc-irqpin-r8a7778",
361 	{ .compatible = "renesas,intc-irqpin-r8a7779",
363 	{ .compatible = "renesas,intc-irqpin-r8a7740",
365 	{ .compatible = "renesas,intc-irqpin-sh73a0",
374 	struct device *dev = &pdev->dev;  in intc_irqpin_probe()
390 		return -ENOMEM;  in intc_irqpin_probe()
393 	of_property_read_u32(dev->of_node, "sense-bitfield-width",  in intc_irqpin_probe()
394 			     &p->sense_bitfield_width);  in intc_irqpin_probe()
395 	control_parent = of_property_read_bool(dev->of_node, "control-parent");  in intc_irqpin_probe()
396 	if (!p->sense_bitfield_width)  in intc_irqpin_probe()
397 		p->sense_bitfield_width = 4; /* default to 4 bits */  in intc_irqpin_probe()
399 	p->pdev = pdev;  in intc_irqpin_probe()
413 			ret = -EINVAL;  in intc_irqpin_probe()
421 		if (ret == -ENXIO)  in intc_irqpin_probe()
426 		p->irq[k].p = p;  in intc_irqpin_probe()
427 		p->irq[k].requested_irq = ret;  in intc_irqpin_probe()
433 		ret = -EINVAL;  in intc_irqpin_probe()
439 		i = &p->iomem[k];  in intc_irqpin_probe()
447 			i->width = 8;  in intc_irqpin_probe()
448 			i->read = intc_irqpin_read8;  in intc_irqpin_probe()
449 			i->write = intc_irqpin_write8;  in intc_irqpin_probe()
452 			i->width = 32;  in intc_irqpin_probe()
453 			i->read = intc_irqpin_read32;  in intc_irqpin_probe()
454 			i->write = intc_irqpin_write32;  in intc_irqpin_probe()
458 			ret = -EINVAL;  in intc_irqpin_probe()
462 		i->iomem = devm_ioremap(dev, io[k]->start,  in intc_irqpin_probe()
464 		if (!i->iomem) {  in intc_irqpin_probe()
466 			ret = -ENXIO;  in intc_irqpin_probe()
472 	if (config && config->irlm_bit >= 0) {  in intc_irqpin_probe()
475 						      config->irlm_bit, 1, 1);  in intc_irqpin_probe()
488 	ref_irq = p->irq[0].requested_irq;  in intc_irqpin_probe()
489 	p->shared_irqs = 1;  in intc_irqpin_probe()
491 		if (ref_irq != p->irq[k].requested_irq) {  in intc_irqpin_probe()
492 			p->shared_irqs = 0;  in intc_irqpin_probe()
501 	} else if (!p->shared_irqs) {  in intc_irqpin_probe()
509 	irq_chip = &p->irq_chip;  in intc_irqpin_probe()
510 	irq_chip->name = "intc-irqpin";  in intc_irqpin_probe()
511 	irq_chip->irq_mask = disable_fn;  in intc_irqpin_probe()
512 	irq_chip->irq_unmask = enable_fn;  in intc_irqpin_probe()
513 	irq_chip->irq_set_type = intc_irqpin_irq_set_type;  in intc_irqpin_probe()
514 	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;  in intc_irqpin_probe()
515 	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;  in intc_irqpin_probe()
517 	p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,  in intc_irqpin_probe()
519 	if (!p->irq_domain) {  in intc_irqpin_probe()
520 		ret = -ENXIO;  in intc_irqpin_probe()
525 	irq_domain_set_pm_device(p->irq_domain, dev);  in intc_irqpin_probe()
527 	if (p->shared_irqs) {  in intc_irqpin_probe()
529 		if (devm_request_irq(dev, p->irq[0].requested_irq,  in intc_irqpin_probe()
533 			ret = -ENOENT;  in intc_irqpin_probe()
539 			if (devm_request_irq(dev, p->irq[k].requested_irq,  in intc_irqpin_probe()
541 					     &p->irq[k])) {  in intc_irqpin_probe()
543 				ret = -ENOENT;  in intc_irqpin_probe()
558 	irq_domain_remove(p->irq_domain);  in intc_irqpin_probe()
569 	irq_domain_remove(p->irq_domain);  in intc_irqpin_remove()
570 	pm_runtime_put(&pdev->dev);  in intc_irqpin_remove()
571 	pm_runtime_disable(&pdev->dev);  in intc_irqpin_remove()
579 	if (atomic_read(&p->wakeup_path))  in intc_irqpin_suspend()