62 static struct icu_chip_data icu_data[MAX_ICU_NR];  variable
75 	if (data == &icu_data[0]) {  in icu_mask_ack_irq()
99 	if (data == &icu_data[0]) {  in icu_mask_irq()
128 	if (data == &icu_data[0]) {  in icu_unmask_irq()
158 		if (irq == icu_data[i].cascade_irq) {  in icu_mux_irq_demux()
159 			domain = icu_data[i].domain;  in icu_mux_irq_demux()
175 			generic_handle_irq(icu_data[i].virq_base + n);  in icu_mux_irq_demux()
233 	generic_handle_domain_irq(icu_data[0].domain, hwirq);  in mmp_handle_irq()
244 	generic_handle_domain_irq(icu_data[0].domain, hwirq);  in mmp2_handle_irq()
254 	icu_data[0].conf_enable = mmp_conf.conf_enable;  in icu_init_irq()
255 	icu_data[0].conf_disable = mmp_conf.conf_disable;  in icu_init_irq()
256 	icu_data[0].conf_mask = mmp_conf.conf_mask;  in icu_init_irq()
257 	icu_data[0].nr_irqs = 64;  in icu_init_irq()
258 	icu_data[0].virq_base = 0;  in icu_init_irq()
259 	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,  in icu_init_irq()
261 						   &icu_data[0]);  in icu_init_irq()
266 	irq_set_default_host(icu_data[0].domain);  in icu_init_irq()
277 	icu_data[0].conf_enable = mmp2_conf.conf_enable;  in mmp2_init_icu()
278 	icu_data[0].conf_disable = mmp2_conf.conf_disable;  in mmp2_init_icu()
279 	icu_data[0].conf_mask = mmp2_conf.conf_mask;  in mmp2_init_icu()
280 	icu_data[0].nr_irqs = 64;  in mmp2_init_icu()
281 	icu_data[0].virq_base = 0;  in mmp2_init_icu()
282 	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,  in mmp2_init_icu()
284 						   &icu_data[0]);  in mmp2_init_icu()
285 	icu_data[1].reg_status = mmp_icu_base + 0x150;  in mmp2_init_icu()
286 	icu_data[1].reg_mask = mmp_icu_base + 0x168;  in mmp2_init_icu()
287 	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +  in mmp2_init_icu()
288 				icu_data[0].nr_irqs;  in mmp2_init_icu()
289 	icu_data[1].clr_mfp_hwirq = 1;		/* offset to IRQ_MMP2_PMIC_BASE */  in mmp2_init_icu()
290 	icu_data[1].nr_irqs = 2;  in mmp2_init_icu()
291 	icu_data[1].cascade_irq = 4;  in mmp2_init_icu()
292 	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;  in mmp2_init_icu()
293 	icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,  in mmp2_init_icu()
294 						   icu_data[1].virq_base, 0,  in mmp2_init_icu()
296 						   &icu_data[1]);  in mmp2_init_icu()
297 	icu_data[2].reg_status = mmp_icu_base + 0x154;  in mmp2_init_icu()
298 	icu_data[2].reg_mask = mmp_icu_base + 0x16c;  in mmp2_init_icu()
299 	icu_data[2].nr_irqs = 2;  in mmp2_init_icu()
300 	icu_data[2].cascade_irq = 5;  in mmp2_init_icu()
301 	icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;  in mmp2_init_icu()
302 	icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,  in mmp2_init_icu()
303 						   icu_data[2].virq_base, 0,  in mmp2_init_icu()
305 						   &icu_data[2]);  in mmp2_init_icu()
306 	icu_data[3].reg_status = mmp_icu_base + 0x180;  in mmp2_init_icu()
307 	icu_data[3].reg_mask = mmp_icu_base + 0x17c;  in mmp2_init_icu()
308 	icu_data[3].nr_irqs = 3;  in mmp2_init_icu()
309 	icu_data[3].cascade_irq = 9;  in mmp2_init_icu()
310 	icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;  in mmp2_init_icu()
311 	icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,  in mmp2_init_icu()
312 						   icu_data[3].virq_base, 0,  in mmp2_init_icu()
314 						   &icu_data[3]);  in mmp2_init_icu()
315 	icu_data[4].reg_status = mmp_icu_base + 0x158;  in mmp2_init_icu()
316 	icu_data[4].reg_mask = mmp_icu_base + 0x170;  in mmp2_init_icu()
317 	icu_data[4].nr_irqs = 5;  in mmp2_init_icu()
318 	icu_data[4].cascade_irq = 17;  in mmp2_init_icu()
319 	icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;  in mmp2_init_icu()
320 	icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,  in mmp2_init_icu()
321 						   icu_data[4].virq_base, 0,  in mmp2_init_icu()
323 						   &icu_data[4]);  in mmp2_init_icu()
324 	icu_data[5].reg_status = mmp_icu_base + 0x15c;  in mmp2_init_icu()
325 	icu_data[5].reg_mask = mmp_icu_base + 0x174;  in mmp2_init_icu()
326 	icu_data[5].nr_irqs = 15;  in mmp2_init_icu()
327 	icu_data[5].cascade_irq = 35;  in mmp2_init_icu()
328 	icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;  in mmp2_init_icu()
329 	icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,  in mmp2_init_icu()
330 						   icu_data[5].virq_base, 0,  in mmp2_init_icu()
332 						   &icu_data[5]);  in mmp2_init_icu()
333 	icu_data[6].reg_status = mmp_icu_base + 0x160;  in mmp2_init_icu()
334 	icu_data[6].reg_mask = mmp_icu_base + 0x178;  in mmp2_init_icu()
335 	icu_data[6].nr_irqs = 2;  in mmp2_init_icu()
336 	icu_data[6].cascade_irq = 51;  in mmp2_init_icu()
337 	icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;  in mmp2_init_icu()
338 	icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,  in mmp2_init_icu()
339 						   icu_data[6].virq_base, 0,  in mmp2_init_icu()
341 						   &icu_data[6]);  in mmp2_init_icu()
342 	icu_data[7].reg_status = mmp_icu_base + 0x188;  in mmp2_init_icu()
343 	icu_data[7].reg_mask = mmp_icu_base + 0x184;  in mmp2_init_icu()
344 	icu_data[7].nr_irqs = 2;  in mmp2_init_icu()
345 	icu_data[7].cascade_irq = 55;  in mmp2_init_icu()
346 	icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;  in mmp2_init_icu()
347 	icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,  in mmp2_init_icu()
348 						   icu_data[7].virq_base, 0,  in mmp2_init_icu()
350 						   &icu_data[7]);  in mmp2_init_icu()
351 	end = icu_data[7].virq_base + icu_data[7].nr_irqs;  in mmp2_init_icu()
354 		if (irq == icu_data[1].cascade_irq ||  in mmp2_init_icu()
355 		    irq == icu_data[2].cascade_irq ||  in mmp2_init_icu()
356 		    irq == icu_data[3].cascade_irq ||  in mmp2_init_icu()
357 		    irq == icu_data[4].cascade_irq ||  in mmp2_init_icu()
358 		    irq == icu_data[5].cascade_irq ||  in mmp2_init_icu()
359 		    irq == icu_data[6].cascade_irq ||  in mmp2_init_icu()
360 		    irq == icu_data[7].cascade_irq) {  in mmp2_init_icu()
368 	irq_set_default_host(icu_data[0].domain);  in mmp2_init_icu()
389 	icu_data[0].virq_base = 0;  in mmp_init_bases()
390 	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,  in mmp_init_bases()
392 						   &icu_data[0]);  in mmp_init_bases()
394 		ret = irq_create_mapping(icu_data[0].domain, irq);  in mmp_init_bases()
400 			icu_data[0].virq_base = ret;  in mmp_init_bases()
402 	icu_data[0].nr_irqs = nr_irqs;  in mmp_init_bases()
405 	if (icu_data[0].virq_base) {  in mmp_init_bases()
407 			irq_dispose_mapping(icu_data[0].virq_base + i);  in mmp_init_bases()
409 	irq_domain_remove(icu_data[0].domain);  in mmp_init_bases()
423 	icu_data[0].conf_enable = mmp_conf.conf_enable;  in mmp_of_init()
424 	icu_data[0].conf_disable = mmp_conf.conf_disable;  in mmp_of_init()
425 	icu_data[0].conf_mask = mmp_conf.conf_mask;  in mmp_of_init()
441 	icu_data[0].conf_enable = mmp2_conf.conf_enable;  in mmp2_of_init()
442 	icu_data[0].conf_disable = mmp2_conf.conf_disable;  in mmp2_of_init()
443 	icu_data[0].conf_mask = mmp2_conf.conf_mask;  in mmp2_of_init()
467 	icu_data[0].conf_enable = mmp3_conf.conf_enable;  in mmp3_of_init()
468 	icu_data[0].conf_disable = mmp3_conf.conf_disable;  in mmp3_of_init()
469 	icu_data[0].conf_mask = mmp3_conf.conf_mask;  in mmp3_of_init()
470 	icu_data[0].conf2_mask = mmp3_conf.conf2_mask;  in mmp3_of_init()
513 	icu_data[i].reg_status = mmp_icu_base + reg[0];  in mmp2_mux_of_init()
514 	icu_data[i].reg_mask = mmp_icu_base + reg[2];  in mmp2_mux_of_init()
515 	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);  in mmp2_mux_of_init()
516 	if (!icu_data[i].cascade_irq)  in mmp2_mux_of_init()
519 	icu_data[i].virq_base = 0;  in mmp2_mux_of_init()
520 	icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,  in mmp2_mux_of_init()
522 						   &icu_data[i]);  in mmp2_mux_of_init()
524 		ret = irq_create_mapping(icu_data[i].domain, irq);  in mmp2_mux_of_init()
530 			icu_data[i].virq_base = ret;  in mmp2_mux_of_init()
532 	icu_data[i].nr_irqs = nr_irqs;  in mmp2_mux_of_init()
535 		icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;  in mmp2_mux_of_init()
536 		icu_data[i].clr_mfp_hwirq = mfp_irq;  in mmp2_mux_of_init()
538 	irq_set_chained_handler(icu_data[i].cascade_irq,  in mmp2_mux_of_init()
543 	if (icu_data[i].virq_base) {  in mmp2_mux_of_init()
545 			irq_dispose_mapping(icu_data[i].virq_base + j);  in mmp2_mux_of_init()
547 	irq_domain_remove(icu_data[i].domain);  in mmp2_mux_of_init()