6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
35 /* Add 2 to convert GIC CPU pin to core interrupt */
38 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
41 /* Convert between local/shared IRQ number and GIC HW IRQ number. */
44 #define GIC_HWIRQ_TO_LOCAL(x)	((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x)	((x) - GIC_SHARED_HWIRQ_BASE)
106 	irq -= GIC_PIN_TO_VEC_OFFSET;  in gic_bind_eic_interrupt()
132 			return -1;  in gic_get_c0_perfcount_int()
144 			return -1;  in gic_get_c0_fdc_int()
158 	/* Get per-cpu bitmaps */  in gic_handle_shared_int()
182 	unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_mask_irq()
190 	unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_unmask_irq()
202 	unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_ack_irq()
212 	irq = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_set_type()
263 	unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);  in gic_set_affinity()
269 		return -EINVAL;  in gic_set_affinity()
274 	/* Re-route this IRQ */  in gic_set_affinity()
290 	.name			=	"MIPS GIC",
300 	.name			=	"MIPS GIC",
333 	int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_mask_local_irq()
340 	int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_unmask_local_irq()
346 	.name			=	"MIPS GIC Local",
357 	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_mask_local_irq_all_vpes()
359 	cd->mask = false;  in gic_mask_local_irq_all_vpes()
375 	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);  in gic_unmask_local_irq_all_vpes()
377 	cd->mask = true;  in gic_unmask_local_irq_all_vpes()
404 		write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);  in gic_all_vpes_irq_cpu_online()
405 		if (cd->mask)  in gic_all_vpes_irq_cpu_online()
413 	.name			= "MIPS GIC Local",
454 		return -EINVAL;  in gic_irq_domain_xlate()
461 		return -EINVAL;  in gic_irq_domain_xlate()
480 			return -EBUSY;  in gic_irq_domain_map()
497 	 * If adding support for more per-cpu interrupts, keep the the  in gic_irq_domain_map()
509 		 * the rest of the MIPS kernel code does not use the  in gic_irq_domain_map()
513 		cd->map = map;  in gic_irq_domain_map()
536 		return -EPERM;  in gic_irq_domain_map()
554 	if (fwspec->param[0] == GIC_SHARED)  in gic_irq_domain_alloc()
555 		hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);  in gic_irq_domain_alloc()
557 		hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);  in gic_irq_domain_alloc()
600 		return -ENOMEM;  in gic_ipi_domain_alloc()
605 			return -EBUSY;  in gic_ipi_domain_alloc()
620 		ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,  in gic_ipi_domain_alloc()
664 		is_ipi = d->bus_token == bus_token;  in gic_ipi_domain_match()
665 		return (!node || to_of_node(d->fwnode) == node) && is_ipi;  in gic_ipi_domain_match()
690 		return -ENXIO;  in gic_register_ipi_domain()
696 	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {  in gic_register_ipi_domain()
701 		 * meeting the requirements of arch/mips SMP.  in gic_register_ipi_domain()
704 		bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);  in gic_register_ipi_domain()
749 	while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",  in gic_of_init()
756 		return -ENODEV;  in gic_of_init()
761 		 * Probe the CM for the GIC base address if not specified  in gic_of_init()
762 		 * in the device-tree.  in gic_of_init()
772 			return -ENODEV;  in gic_of_init()
781 		/* Ensure GIC region is enabled before trying to access it */  in gic_of_init()
788 		return -ENOMEM;  in gic_of_init()
802 		gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;  in gic_of_init()
808 		 * waiting poll loop. We must not re-route those CPU's local  in gic_of_init()
833 		return -ENXIO;  in gic_of_init()
850 				 "irqchip/mips/gic:starting",  in gic_of_init()
853 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);