Lines Matching full:gic
5 * Interrupt architecture for the GIC:
41 #include <linux/irqchip/arm-gic.h>
49 #include "irq-gic-common.h"
113 * The GIC mapping of CPU interfaces does not necessarily match
115 * by the GIC itself.
311 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
320 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
355 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
363 * The GIC encodes the source CPU in GICC_IAR, in gic_handle_irq()
372 generic_handle_domain_irq(gic->domain, irqnr); in gic_handle_irq()
402 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_irq_print_chip() local
404 if (gic->domain->dev) in gic_irq_print_chip()
405 seq_printf(p, gic->domain->dev->of_node->name); in gic_irq_print_chip()
407 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0])); in gic_irq_print_chip()
417 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
419 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask()
431 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); in gic_get_cpumask()
442 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument
444 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_cpu_if_up()
449 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) in gic_cpu_if_up()
466 static void gic_dist_init(struct gic_chip_data *gic) in gic_dist_init() argument
470 unsigned int gic_irqs = gic->gic_irqs; in gic_dist_init()
471 void __iomem *base = gic_data_dist_base(gic); in gic_dist_init()
478 cpumask = gic_get_cpumask(gic); in gic_dist_init()
489 static int gic_cpu_init(struct gic_chip_data *gic) in gic_cpu_init() argument
491 void __iomem *dist_base = gic_data_dist_base(gic); in gic_cpu_init()
492 void __iomem *base = gic_data_cpu_base(gic); in gic_cpu_init()
497 * Setting up the CPU map is only relevant for the primary GIC in gic_cpu_init()
501 if (gic == &gic_data[0]) { in gic_cpu_init()
503 * Get what the GIC says our CPU mask is. in gic_cpu_init()
509 cpu_mask = gic_get_cpumask(gic); in gic_cpu_init()
524 gic_cpu_if_up(gic); in gic_cpu_init()
547 * Saves the GIC distributor registers during suspend or idle. Must be called
548 * with interrupts disabled but before powering down the GIC. After calling
549 * this function, no interrupts will be delivered by the GIC, and another
552 void gic_dist_save(struct gic_chip_data *gic) in gic_dist_save() argument
558 if (WARN_ON(!gic)) in gic_dist_save()
561 gic_irqs = gic->gic_irqs; in gic_dist_save()
562 dist_base = gic_data_dist_base(gic); in gic_dist_save()
568 gic->saved_spi_conf[i] = in gic_dist_save()
572 gic->saved_spi_target[i] = in gic_dist_save()
576 gic->saved_spi_enable[i] = in gic_dist_save()
580 gic->saved_spi_active[i] = in gic_dist_save()
585 * Restores the GIC distributor registers during resume or when coming out of
587 * that occurred while the GIC was suspended is still present, it will be
589 * the GIC and need to be handled by the platform-specific wakeup source.
591 void gic_dist_restore(struct gic_chip_data *gic) in gic_dist_restore() argument
597 if (WARN_ON(!gic)) in gic_dist_restore()
600 gic_irqs = gic->gic_irqs; in gic_dist_restore()
601 dist_base = gic_data_dist_base(gic); in gic_dist_restore()
609 writel_relaxed(gic->saved_spi_conf[i], in gic_dist_restore()
617 writel_relaxed(gic->saved_spi_target[i], in gic_dist_restore()
623 writel_relaxed(gic->saved_spi_enable[i], in gic_dist_restore()
630 writel_relaxed(gic->saved_spi_active[i], in gic_dist_restore()
637 void gic_cpu_save(struct gic_chip_data *gic) in gic_cpu_save() argument
644 if (WARN_ON(!gic)) in gic_cpu_save()
647 dist_base = gic_data_dist_base(gic); in gic_cpu_save()
648 cpu_base = gic_data_cpu_base(gic); in gic_cpu_save()
653 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_save()
657 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_save()
661 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_save()
667 void gic_cpu_restore(struct gic_chip_data *gic) in gic_cpu_restore() argument
674 if (WARN_ON(!gic)) in gic_cpu_restore()
677 dist_base = gic_data_dist_base(gic); in gic_cpu_restore()
678 cpu_base = gic_data_cpu_base(gic); in gic_cpu_restore()
683 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_restore()
690 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_restore()
697 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_restore()
706 gic_cpu_if_up(gic); in gic_cpu_restore()
739 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
741 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
743 if (WARN_ON(!gic->saved_ppi_enable)) in gic_pm_init()
746 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
748 if (WARN_ON(!gic->saved_ppi_active)) in gic_pm_init()
751 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, in gic_pm_init()
753 if (WARN_ON(!gic->saved_ppi_conf)) in gic_pm_init()
756 if (gic == &gic_data[0]) in gic_pm_init()
762 free_percpu(gic->saved_ppi_active); in gic_pm_init()
764 free_percpu(gic->saved_ppi_enable); in gic_pm_init()
769 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
799 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_set_affinity() local
802 if (unlikely(gic != &gic_data[0])) in gic_set_affinity()
867 "irqchip/arm/gic:starting", in gic_smp_init()
935 * @cpu: the logical CPU number to get the GIC ID for.
1048 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); in gic_init_physaddr()
1059 struct gic_chip_data *gic = d->host_data; in gic_irq_domain_map() local
1064 gic == &gic_data[0]) ? &gic_chip_mode1 : &gic_chip; in gic_irq_domain_map()
1176 static int gic_init_bases(struct gic_chip_data *gic, in gic_init_bases() argument
1181 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1182 /* Frankein-GIC without banked registers... */ in gic_init_bases()
1185 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1186 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1187 if (WARN_ON(!gic->dist_base.percpu_base || in gic_init_bases()
1188 !gic->cpu_base.percpu_base)) { in gic_init_bases()
1196 unsigned long offset = gic->percpu_offset * core_id; in gic_init_bases()
1197 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = in gic_init_bases()
1198 gic->raw_dist_base + offset; in gic_init_bases()
1199 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = in gic_init_bases()
1200 gic->raw_cpu_base + offset; in gic_init_bases()
1205 /* Normal, sane GIC... */ in gic_init_bases()
1206 WARN(gic->percpu_offset, in gic_init_bases()
1208 gic->percpu_offset); in gic_init_bases()
1209 gic->dist_base.common_base = gic->raw_dist_base; in gic_init_bases()
1210 gic->cpu_base.common_base = gic->raw_cpu_base; in gic_init_bases()
1215 * The GIC only supports up to 1020 interrupt sources. in gic_init_bases()
1217 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; in gic_init_bases()
1221 gic->gic_irqs = gic_irqs; in gic_init_bases()
1224 gic->domain = irq_domain_create_linear(handle, gic_irqs, in gic_init_bases()
1226 gic); in gic_init_bases()
1230 * No secondary GIC support whatsoever. in gic_init_bases()
1243 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, in gic_init_bases()
1244 16, &gic_irq_domain_ops, gic); in gic_init_bases()
1247 if (WARN_ON(!gic->domain)) { in gic_init_bases()
1252 gic_dist_init(gic); in gic_init_bases()
1253 ret = gic_cpu_init(gic); in gic_init_bases()
1257 ret = gic_pm_init(gic); in gic_init_bases()
1264 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1265 free_percpu(gic->dist_base.percpu_base); in gic_init_bases()
1266 free_percpu(gic->cpu_base.percpu_base); in gic_init_bases()
1272 static int __init __gic_init_bases(struct gic_chip_data *gic, in __gic_init_bases() argument
1277 if (WARN_ON(!gic || gic->domain)) in __gic_init_bases()
1280 if (gic == &gic_data[0]) { in __gic_init_bases()
1284 * This is only necessary for the primary GIC. in __gic_init_bases()
1291 pr_info("GIC: Using split EOI/Deactivate mode\n"); in __gic_init_bases()
1294 ret = gic_init_bases(gic, handle); in __gic_init_bases()
1295 if (gic == &gic_data[0]) in __gic_init_bases()
1303 struct gic_chip_data *gic; in gic_init() local
1311 gic = &gic_data[0]; in gic_init()
1312 gic->raw_dist_base = dist_base; in gic_init()
1313 gic->raw_cpu_base = cpu_base; in gic_init()
1315 __gic_init_bases(gic, NULL); in gic_init()
1318 static void gic_teardown(struct gic_chip_data *gic) in gic_teardown() argument
1320 if (WARN_ON(!gic)) in gic_teardown()
1323 if (gic->raw_dist_base) in gic_teardown()
1324 iounmap(gic->raw_dist_base); in gic_teardown()
1325 if (gic->raw_cpu_base) in gic_teardown()
1326 iounmap(gic->raw_cpu_base); in gic_teardown()
1357 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1370 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1387 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1410 pr_warn("GIC: Adjusting CPU interface base to %pa\n", in gic_check_eoimode()
1441 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) in gic_of_setup() argument
1443 if (!gic || !node) in gic_of_setup()
1446 gic->raw_dist_base = of_iomap(node, 0); in gic_of_setup()
1447 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) in gic_of_setup()
1450 gic->raw_cpu_base = of_iomap(node, 1); in gic_of_setup()
1451 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) in gic_of_setup()
1454 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) in gic_of_setup()
1455 gic->percpu_offset = 0; in gic_of_setup()
1457 gic_enable_of_quirks(node, gic_quirks, gic); in gic_of_setup()
1462 gic_teardown(gic); in gic_of_setup()
1467 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1471 if (!dev || !dev->of_node || !gic || !irq) in gic_of_init_child()
1474 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); in gic_of_init_child()
1475 if (!*gic) in gic_of_init_child()
1478 ret = gic_of_setup(*gic, dev->of_node); in gic_of_init_child()
1482 ret = gic_init_bases(*gic, &dev->of_node->fwnode); in gic_of_init_child()
1484 gic_teardown(*gic); in gic_of_init_child()
1488 irq_domain_set_pm_device((*gic)->domain, dev); in gic_of_init_child()
1489 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); in gic_of_init_child()
1521 struct gic_chip_data *gic; in gic_of_init() local
1530 gic = &gic_data[gic_cnt]; in gic_of_init()
1532 ret = gic_of_setup(gic, node); in gic_of_init()
1540 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) in gic_of_init()
1543 ret = __gic_init_bases(gic, &node->fwnode); in gic_of_init()
1545 gic_teardown(gic); in gic_of_init()
1565 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1566 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1567 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1568 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1569 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1570 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1575 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1696 struct gic_chip_data *gic = &gic_data[0]; in gic_v2_acpi_init() local
1707 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); in gic_v2_acpi_init()
1708 if (!gic->raw_cpu_base) { in gic_v2_acpi_init()
1714 gic->raw_dist_base = ioremap(dist->base_address, in gic_v2_acpi_init()
1716 if (!gic->raw_dist_base) { in gic_v2_acpi_init()
1718 gic_teardown(gic); in gic_v2_acpi_init()
1731 * Initialize GIC instance zero (no multi-GIC support). in gic_v2_acpi_init()
1736 gic_teardown(gic); in gic_v2_acpi_init()
1740 ret = __gic_init_bases(gic, gsi_domain_handle); in gic_v2_acpi_init()
1742 pr_err("Failed to initialise GIC\n"); in gic_v2_acpi_init()
1744 gic_teardown(gic); in gic_v2_acpi_init()