1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70  * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74  * When security is enabled, non-secure priority values from the (re)distributor
78  * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
84  * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
86  * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
104  * When the Non-secure world has access to group 0 interrupts (as a
109  * written by software is moved to the Non-secure range by the Distributor.
124 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
132 #define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
170 	return __get_intid_range(d->hwirq);  in get_intid_range()
175 	return d->hwirq;  in gic_irq()
196 		/* SGI+PPI -> SGI_base for this CPU */  in gic_dist_base()
201 		/* SPI -> dist_base */  in gic_dist_base()
214 		count--;  in gic_do_wait_for_rwp()
272 	while (--count) {  in gic_enable_redist()
293 		*index = d->hwirq;  in convert_offset_index()
298 		 * to the PPI range in the registers, so let's adjust the  in convert_offset_index()
301 		*index = d->hwirq - EPPI_BASE_INTID + 32;  in convert_offset_index()
304 		*index = d->hwirq - ESPI_BASE_INTID;  in convert_offset_index()
333 	*index = d->hwirq;  in convert_offset_index()
409 	if (d->hwirq >= 8192) /* SGI/PPI/SPI only */  in gic_irq_set_irqchip_state()
410 		return -EINVAL;  in gic_irq_set_irqchip_state()
430 		return -EINVAL;  in gic_irq_set_irqchip_state()
440 	if (d->hwirq >= 8192) /* PPI/SPI only */  in gic_irq_get_irqchip_state()
441 		return -EINVAL;  in gic_irq_get_irqchip_state()
457 		return -EINVAL;  in gic_irq_get_irqchip_state()
477 		return hwirq - 16;  in __gic_get_ppi_index()
479 		return hwirq - EPPI_BASE_INTID + 16;  in __gic_get_ppi_index()
487 	return __gic_get_ppi_index(d->hwirq);  in gic_get_ppi_index()
492 	struct irq_desc *desc = irq_to_desc(d->irq);  in gic_irq_nmi_setup()
495 		return -EINVAL;  in gic_irq_nmi_setup()
498 		pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);  in gic_irq_nmi_setup()
499 		return -EINVAL;  in gic_irq_nmi_setup()
507 		return -EINVAL;  in gic_irq_nmi_setup()
513 		/* Setting up PPI as NMI, only switch handler for first NMI */  in gic_irq_nmi_setup()
516 			desc->handle_irq = handle_percpu_devid_fasteoi_nmi;  in gic_irq_nmi_setup()
519 		desc->handle_irq = handle_fasteoi_nmi;  in gic_irq_nmi_setup()
529 	struct irq_desc *desc = irq_to_desc(d->irq);  in gic_irq_nmi_teardown()
535 		pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);  in gic_irq_nmi_teardown()
552 			desc->handle_irq = handle_percpu_devid_irq;  in gic_irq_nmi_teardown()
554 		desc->handle_irq = handle_fasteoi_irq;  in gic_irq_nmi_teardown()
589 		return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;  in gic_set_type()
594 		return -EINVAL;  in gic_set_type()
606 		pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);  in gic_set_type()
616 		return -EINVAL;  in gic_irq_set_vcpu_affinity()
709 		WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr);  in __gic_handle_nmi()
814 	 * setting the highest possible, non-zero priority in PMR.  in gic_has_group0()
818 	 * actual priority in the non-secure range. In the process, it  in gic_has_group0()
823 	gic_write_pmr(BIT(8 - gic_get_pribits()));  in gic_has_group0()
843 	 * Configure SPIs as non-secure Group-1. This will only matter  in gic_dist_init()
893 	int ret = -ENODEV;  in gic_iterate_rdists()
927 	return ret ? -ENODEV : 0;  in gic_iterate_rdists()
947 		u64 offset = ptr - region->redist_base;  in __gic_populate_rdist()
948 		raw_spin_lock_init(&gic_data_rdist()->rd_lock);  in __gic_populate_rdist()
950 		gic_data_rdist()->phys_base = region->phys_base + offset;  in __gic_populate_rdist()
954 			(int)(region - gic_data.redist_regions),  in __gic_populate_rdist()
955 			&gic_data_rdist()->phys_base);  in __gic_populate_rdist()
969 	WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",  in gic_populate_rdist()
972 	return -ENODEV;  in gic_populate_rdist()
981 	/* Boot-time cleanup */  in __gic_update_rdist_properties()
1001 	 * doc says... :-/ And CTLR.IR implies another subset of DirectLPI  in __gic_update_rdist_properties()
1014 	/* Detect non-sensical configurations */  in __gic_update_rdist_properties()
1094 	 * any pre-emptive interrupts from working at all). Writing a zero  in gic_cpu_sys_reg_init()
1163 	 *   - The write is ignored.  in gic_cpu_sys_reg_init()
1164 	 *   - The RS field is treated as 0.  in gic_cpu_sys_reg_init()
1203 	/* Configure SGIs/PPIs as non-secure Group-1 */  in gic_cpu_init()
1246 			cpu--;  in gic_compute_target_list()
1278 	if (WARN_ON(d->hwirq >= 16))  in gic_ipi_send_mask()
1292 		gic_send_sgi(cluster_id, tlist, d->hwirq);  in gic_ipi_send_mask()
1311 	/* Register all 8 non-secure SGIs */  in gic_smp_init()
1312 	base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,  in gic_smp_init()
1336 		return -EINVAL;  in gic_set_affinity()
1339 		return -EINVAL;  in gic_set_affinity()
1453 		irq_domain_set_info(d, irq, hw, chip, d->host_data,  in gic_irq_domain_map()
1459 		irq_domain_set_info(d, irq, hw, chip, d->host_data,  in gic_irq_domain_map()
1467 			return -EPERM;  in gic_irq_domain_map()
1468 		irq_domain_set_info(d, irq, hw, chip, d->host_data,  in gic_irq_domain_map()
1473 		return -EPERM;  in gic_irq_domain_map()
1486 	if (fwspec->param_count == 1 && fwspec->param[0] < 16) {  in gic_irq_domain_translate()
1487 		*hwirq = fwspec->param[0];  in gic_irq_domain_translate()
1492 	if (is_of_node(fwspec->fwnode)) {  in gic_irq_domain_translate()
1493 		if (fwspec->param_count < 3)  in gic_irq_domain_translate()
1494 			return -EINVAL;  in gic_irq_domain_translate()
1496 		switch (fwspec->param[0]) {  in gic_irq_domain_translate()
1498 			*hwirq = fwspec->param[1] + 32;  in gic_irq_domain_translate()
1500 		case 1:			/* PPI */  in gic_irq_domain_translate()
1501 			*hwirq = fwspec->param[1] + 16;  in gic_irq_domain_translate()
1504 			*hwirq = fwspec->param[1] + ESPI_BASE_INTID;  in gic_irq_domain_translate()
1507 			*hwirq = fwspec->param[1] + EPPI_BASE_INTID;  in gic_irq_domain_translate()
1510 			*hwirq = fwspec->param[1];  in gic_irq_domain_translate()
1513 			*hwirq = fwspec->param[1];  in gic_irq_domain_translate()
1514 			if (fwspec->param[1] >= 16)  in gic_irq_domain_translate()
1515 				*hwirq += EPPI_BASE_INTID - 16;  in gic_irq_domain_translate()
1520 			return -EINVAL;  in gic_irq_domain_translate()
1523 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;  in gic_irq_domain_translate()
1530 			fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);  in gic_irq_domain_translate()
1534 	if (is_fwnode_irqchip(fwspec->fwnode)) {  in gic_irq_domain_translate()
1535 		if(fwspec->param_count != 2)  in gic_irq_domain_translate()
1536 			return -EINVAL;  in gic_irq_domain_translate()
1538 		if (fwspec->param[0] < 16) {  in gic_irq_domain_translate()
1540 			       fwspec->param[0]);  in gic_irq_domain_translate()
1541 			return -EINVAL;  in gic_irq_domain_translate()
1544 		*hwirq = fwspec->param[0];  in gic_irq_domain_translate()
1545 		*type = fwspec->param[1];  in gic_irq_domain_translate()
1551 	return -EINVAL;  in gic_irq_domain_translate()
1595 	if (!is_of_node(fwspec->fwnode))  in fwspec_is_partitioned_ppi()
1598 	if (fwspec->param_count < 4 || !fwspec->param[3])  in fwspec_is_partitioned_ppi()
1616         if (fwspec->fwnode != d->fwnode)  in gic_irq_domain_select()
1620 	if (!is_of_node(fwspec->fwnode))  in gic_irq_domain_select()
1631 	 * If this is a PPI and we have a 4th (non-null) parameter,  in gic_irq_domain_select()
1656 		return -ENOMEM;  in partition_domain_translate()
1658 	np = of_find_node_by_phandle(fwspec->param[3]);  in partition_domain_translate()
1660 		return -EINVAL;  in partition_domain_translate()
1673 	*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;  in partition_domain_translate()
1687 	d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;  in gic_enable_quirk_msm8996()
1696 	d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;  in gic_enable_quirk_cavium_38539()
1706 	 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite  in gic_enable_quirk_hip06_07()
1708 	 * that GIC-600 doesn't have ESPI, so nothing to do in that case.  in gic_enable_quirk_hip06_07()
1712 	if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {  in gic_enable_quirk_hip06_07()
1714 		d->rdists.gicd_typer &= ~GENMASK(9, 8);  in gic_enable_quirk_hip06_07()
1724 		.compatible = "qcom,msm8996-gic-v3",
1743 		 * - ThunderX: CN88xx
1744 		 * - OCTEON TX: CN83xx, CN81xx
1745 		 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1778 	pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",  in gic_enable_nmi_support()
1784 	 * and if Group 0 interrupts can be delivered to Linux in the non-secure  in gic_enable_nmi_support()
1790 	 * -----------------------------------------------------------  in gic_enable_nmi_support()
1791 	 *      1       |      -      |  unchanged  |    unchanged  in gic_enable_nmi_support()
1792 	 * -----------------------------------------------------------  in gic_enable_nmi_support()
1793 	 *      0       |      1      |  non-secure |    non-secure  in gic_enable_nmi_support()
1794 	 * -----------------------------------------------------------  in gic_enable_nmi_support()
1795 	 *      0       |      0      |  unchanged  |    non-secure  in gic_enable_nmi_support()
1797 	 * where non-secure means that the value is right-shifted by one and the  in gic_enable_nmi_support()
1798 	 * MSB bit set, to make it fit in the non-secure priority range.  in gic_enable_nmi_support()
1805 	 * be in the non-secure range, we use a different PMR value to mask IRQs  in gic_enable_nmi_support()
1849 	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);  in gic_init_bases()
1868 		err = -ENOMEM;  in gic_init_bases()
1916 		return -ENODEV;  in gic_validate_dist_version()
1921 /* Create all possible partitions at boot time */
1929 	parts_node = of_get_child_by_name(gic_node, "ppi-partitions");  in gic_populate_ppi_partitions()
1952 		part->partition_id = of_node_to_fwnode(child_part);  in gic_populate_ppi_partitions()
1954 		pr_info("GIC: PPI partition %pOFn[%d] { ",  in gic_populate_ppi_partitions()
1983 			cpumask_set_cpu(cpu, &part->mask);  in gic_populate_ppi_partitions()
2031 	if (of_property_read_u32(node, "#redistributor-regions",  in gic_of_setup_kvm_info()
2063 	gic_request_region(res->start, resource_size(res), name);  in gic_of_iomap()
2066 	return base ?: IOMEM_ERR_PTR(-ENOMEM);  in gic_of_iomap()
2090 	if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))  in gic_of_init()
2096 		err = -ENOMEM;  in gic_of_init()
2104 			err = -ENODEV;  in gic_of_init()
2110 	if (of_property_read_u64(node, "redistributor-stride", &redist_stride))  in gic_of_init()
2116 			     redist_stride, &node->fwnode);  in gic_of_init()
2136 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2170 	redist_base = ioremap(redist->base_address, redist->length);  in gic_acpi_parse_madt_redist()
2172 		pr_err("Couldn't map GICR region @%llx\n", redist->base_address);  in gic_acpi_parse_madt_redist()
2173 		return -ENOMEM;  in gic_acpi_parse_madt_redist()
2175 	gic_request_region(redist->base_address, redist->length, "GICR");  in gic_acpi_parse_madt_redist()
2177 	gic_acpi_register_redist(redist->base_address, redist_base);  in gic_acpi_parse_madt_redist()
2192 	if (!(gicc->flags & ACPI_MADT_ENABLED))  in gic_acpi_parse_madt_gicc()
2195 	redist_base = ioremap(gicc->gicr_base_address, size);  in gic_acpi_parse_madt_gicc()
2197 		return -ENOMEM;  in gic_acpi_parse_madt_gicc()
2198 	gic_request_region(gicc->gicr_base_address, size, "GICR");  in gic_acpi_parse_madt_gicc()
2200 	gic_acpi_register_redist(gicc->gicr_base_address, redist_base);  in gic_acpi_parse_madt_gicc()
2222 	return -ENODEV;  in gic_acpi_collect_gicr_base()
2242 	if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {  in gic_acpi_match_gicc()
2251 	if (!(gicc->flags & ACPI_MADT_ENABLED))  in gic_acpi_match_gicc()
2254 	return -ENODEV;  in gic_acpi_match_gicc()
2290 	if (dist->version != ape->driver_data)  in acpi_validate_gic_table()
2311 	if (!(gicc->flags & ACPI_MADT_ENABLED))  in gic_acpi_parse_virt_madt_gicc()
2314 	maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?  in gic_acpi_parse_virt_madt_gicc()
2320 		acpi_data.maint_irq = gicc->vgic_interrupt;  in gic_acpi_parse_virt_madt_gicc()
2322 		acpi_data.vcpu_base = gicc->gicv_base_address;  in gic_acpi_parse_virt_madt_gicc()
2330 	if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||  in gic_acpi_parse_virt_madt_gicc()
2332 	    (acpi_data.vcpu_base != gicc->gicv_base_address))  in gic_acpi_parse_virt_madt_gicc()
2333 		return -EINVAL;  in gic_acpi_parse_virt_madt_gicc()
2374 		vcpu->flags = IORESOURCE_MEM;  in gic_acpi_setup_kvm_info()
2375 		vcpu->start = acpi_data.vcpu_base;  in gic_acpi_setup_kvm_info()
2376 		vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;  in gic_acpi_setup_kvm_info()
2400 	acpi_data.dist_base = ioremap(dist->base_address,  in gic_acpi_init()
2404 		return -ENOMEM;  in gic_acpi_init()
2406 	gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD");  in gic_acpi_init()
2418 		err = -ENOMEM;  in gic_acpi_init()
2426 	gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);  in gic_acpi_init()
2428 		err = -ENOMEM;  in gic_acpi_init()