1 // SPDX-License-Identifier: GPL-2.0-only
19  *   0x1000_0028: CPU0_W0_STATUS		IRQs 31-63
20  *   0x1000_002c: CPU0_W1_STATUS		IRQs 0-31
23  *   0x1000_0038: CPU1_W0_STATUS		IRQs 31-63
24  *   0x1000_003c: CPU1_W1_STATUS		IRQs 0-31
31  *   0x1000_0030: CPU0_W0_STATUS	IRQs 96-127
32  *   0x1000_0034: CPU0_W1_STATUS	IRQs 64-95
33  *   0x1000_0038: CPU0_W2_STATUS	IRQs 32-63
34  *   0x1000_003c: CPU0_W3_STATUS	IRQs 0-31
39  *   0x1000_0050: CPU1_W0_STATUS	IRQs 96-127
40  *   0x1000_0054: CPU1_W1_STATUS	IRQs 64-95
41  *   0x1000_0058: CPU1_W2_STATUS	IRQs 32-63
42  *   0x1000_005c: CPU1_W3_STATUS	IRQs 0-31
44  * IRQs are numbered in CPU native endian order
45  * (which is big-endian in these examples)
94 	return (1 * intc->n_words - word - 1) * sizeof(u32);  in reg_enable()
96 	return (0 * intc->n_words + word) * sizeof(u32);  in reg_enable()
104 	return (2 * intc->n_words - word - 1) * sizeof(u32);  in reg_status()
106 	return (1 * intc->n_words + word) * sizeof(u32);  in reg_status()
113 	return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));  in cpu_for_irq()
116 static void bcm6345_l1_irq_handle(struct irq_desc *desc)  in bcm6345_l1_irq_handle()  argument
118 	struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);  in bcm6345_l1_irq_handle()
120 	struct irq_chip *chip = irq_desc_get_chip(desc);  in bcm6345_l1_irq_handle()
124 	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];  in bcm6345_l1_irq_handle()
126 	cpu = intc->cpus[0];  in bcm6345_l1_irq_handle()
129 	chained_irq_enter(chip, desc);  in bcm6345_l1_irq_handle()
131 	for (idx = 0; idx < intc->n_words; idx++) {  in bcm6345_l1_irq_handle()
136 		pending = __raw_readl(cpu->map_base + reg_status(intc, idx));  in bcm6345_l1_irq_handle()
137 		pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));  in bcm6345_l1_irq_handle()
140 			if (generic_handle_domain_irq(intc->domain, base + hwirq))  in bcm6345_l1_irq_handle()
145 	chained_irq_exit(chip, desc);  in bcm6345_l1_irq_handle()
151 	u32 word = d->hwirq / IRQS_PER_WORD;  in __bcm6345_l1_unmask()
152 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);  in __bcm6345_l1_unmask()
155 	intc->cpus[cpu_idx]->enable_cache[word] |= mask;  in __bcm6345_l1_unmask()
156 	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],  in __bcm6345_l1_unmask()
157 		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));  in __bcm6345_l1_unmask()
163 	u32 word = d->hwirq / IRQS_PER_WORD;  in __bcm6345_l1_mask()
164 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);  in __bcm6345_l1_mask()
167 	intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;  in __bcm6345_l1_mask()
168 	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],  in __bcm6345_l1_mask()
169 		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));  in __bcm6345_l1_mask()
177 	raw_spin_lock_irqsave(&intc->lock, flags);  in bcm6345_l1_unmask()
179 	raw_spin_unlock_irqrestore(&intc->lock, flags);  in bcm6345_l1_unmask()
187 	raw_spin_lock_irqsave(&intc->lock, flags);  in bcm6345_l1_mask()
189 	raw_spin_unlock_irqrestore(&intc->lock, flags);  in bcm6345_l1_mask()
197 	u32 word = d->hwirq / IRQS_PER_WORD;  in bcm6345_l1_set_affinity()
198 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);  in bcm6345_l1_set_affinity()
205 	if (!cpumask_and(&valid, &intc->cpumask, dest))  in bcm6345_l1_set_affinity()
206 		return -EINVAL;  in bcm6345_l1_set_affinity()
210 		return -EINVAL;  in bcm6345_l1_set_affinity()
214 	raw_spin_lock_irqsave(&intc->lock, flags);  in bcm6345_l1_set_affinity()
216 		enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;  in bcm6345_l1_set_affinity()
225 	raw_spin_unlock_irqrestore(&intc->lock, flags);  in bcm6345_l1_set_affinity()
242 		return -EINVAL;  in bcm6345_l1_init_one()
246 	if (!intc->n_words)  in bcm6345_l1_init_one()
247 		intc->n_words = n_words;  in bcm6345_l1_init_one()
248 	else if (intc->n_words != n_words)  in bcm6345_l1_init_one()
249 		return -EINVAL;  in bcm6345_l1_init_one()
251 	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),  in bcm6345_l1_init_one()
254 		return -ENOMEM;  in bcm6345_l1_init_one()
256 	cpu->map_base = ioremap(res.start, sz);  in bcm6345_l1_init_one()
257 	if (!cpu->map_base)  in bcm6345_l1_init_one()
258 		return -ENOMEM;  in bcm6345_l1_init_one()
261 		cpu->enable_cache[i] = 0;  in bcm6345_l1_init_one()
262 		__raw_writel(0, cpu->map_base + reg_enable(intc, i));  in bcm6345_l1_init_one()
265 	cpu->parent_irq = irq_of_parse_and_map(dn, idx);  in bcm6345_l1_init_one()
266 	if (!cpu->parent_irq) {  in bcm6345_l1_init_one()
267 		pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);  in bcm6345_l1_init_one()
268 		return -EINVAL;  in bcm6345_l1_init_one()
270 	irq_set_chained_handler_and_data(cpu->parent_irq,  in bcm6345_l1_init_one()
277 	.name			= "bcm6345-l1",
288 	irq_set_chip_data(virq, d->host_data);  in bcm6345_l1_map()
307 		return -ENOMEM;  in bcm6345_l1_of_init()
315 			cpumask_set_cpu(idx, &intc->cpumask);  in bcm6345_l1_of_init()
318 	if (cpumask_empty(&intc->cpumask)) {  in bcm6345_l1_of_init()
319 		ret = -ENODEV;  in bcm6345_l1_of_init()
323 	raw_spin_lock_init(&intc->lock);  in bcm6345_l1_of_init()
325 	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,  in bcm6345_l1_of_init()
328 	if (!intc->domain) {  in bcm6345_l1_of_init()
329 		ret = -ENOMEM;  in bcm6345_l1_of_init()
334 			IRQS_PER_WORD * intc->n_words);  in bcm6345_l1_of_init()
335 	for_each_cpu(idx, &intc->cpumask) {  in bcm6345_l1_of_init()
336 		struct bcm6345_l1_cpu *cpu = intc->cpus[idx];  in bcm6345_l1_of_init()
339 				cpu->map_base, cpu->parent_irq);  in bcm6345_l1_of_init()
346 		struct bcm6345_l1_cpu *cpu = intc->cpus[idx];  in bcm6345_l1_of_init()
349 			if (cpu->map_base)  in bcm6345_l1_of_init()
350 				iounmap(cpu->map_base);  in bcm6345_l1_of_init()
359 IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);