73 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0);  in aic5_handle()  local
77 	irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);  in aic5_handle()
78 	irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);  in aic5_handle()
81 		irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);  in aic5_handle()
89 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_mask()  local
96 	irq_gc_lock(bgc);  in aic5_mask()
100 	irq_gc_unlock(bgc);  in aic5_mask()
106 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_unmask()  local
113 	irq_gc_lock(bgc);  in aic5_unmask()
117 	irq_gc_unlock(bgc);  in aic5_unmask()
123 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_retrigger()  local
126 	irq_gc_lock(bgc);  in aic5_retrigger()
127 	irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);  in aic5_retrigger()
128 	irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);  in aic5_retrigger()
129 	irq_gc_unlock(bgc);  in aic5_retrigger()
137 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_set_type()  local
141 	irq_gc_lock(bgc);  in aic5_set_type()
142 	irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);  in aic5_set_type()
143 	smr = irq_reg_readl(bgc, AT91_AIC5_SMR);  in aic5_set_type()
146 		irq_reg_writel(bgc, smr, AT91_AIC5_SMR);  in aic5_set_type()
147 	irq_gc_unlock(bgc);  in aic5_set_type()
159 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_suspend()  local
166 			irq_reg_writel(bgc, i, AT91_AIC5_SSR);  in aic5_suspend()
167 			smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);  in aic5_suspend()
170 	irq_gc_lock(bgc);  in aic5_suspend()
176 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
178 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_suspend()
180 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_suspend()
182 	irq_gc_unlock(bgc);  in aic5_suspend()
189 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_resume()  local
194 	irq_gc_lock(bgc);  in aic5_resume()
197 		irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);  in aic5_resume()
199 			irq_reg_writel(bgc, i, AT91_AIC5_SSR);  in aic5_resume()
200 			irq_reg_writel(bgc, i, AT91_AIC5_SVR);  in aic5_resume()
201 			irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);  in aic5_resume()
212 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
214 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_resume()
216 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_resume()
218 	irq_gc_unlock(bgc);  in aic5_resume()
225 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_pm_shutdown()  local
229 	irq_gc_lock(bgc);  in aic5_pm_shutdown()
231 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
232 		irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_pm_shutdown()
233 		irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);  in aic5_pm_shutdown()
235 	irq_gc_unlock(bgc);  in aic5_pm_shutdown()
280 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0);  in aic5_irq_domain_xlate()  local
285 	if (!bgc)  in aic5_irq_domain_xlate()
293 	irq_gc_lock_irqsave(bgc, flags);  in aic5_irq_domain_xlate()
294 	irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);  in aic5_irq_domain_xlate()
295 	smr = irq_reg_readl(bgc, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()
297 	irq_reg_writel(bgc, smr, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()
298 	irq_gc_unlock_irqrestore(bgc, flags);  in aic5_irq_domain_xlate()