7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
23 #include <linux/cpu.h>
40  *    To CPU 0                 To CPU 1
44  * +---------------+     +---------------+
46  * |    per-CPU    |	 |    per-CPU    |
50  * +---------------+	 +---------------+
55  *            +-------------------+
60  *            +-------------------+
71  * The "per-CPU mask/unmask" is modified using the
75  * which automatically accesses the registers of the current CPU.
77  * The per-CPU mask/unmask can also be adjusted using the global
78  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
82  * different levels: at the global level and at the per-CPU level.
86  *  - For global interrupts:
88  *    At ->map() time, a global interrupt is unmasked at the per-CPU
90  *    the current CPU, running the ->map() code. This allows to have
91  *    the interrupt unmasked at this level in non-SMP
92  *    configurations. In SMP configurations, the ->set_affinity()
94  *    ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
97  *    The ->mask() and ->unmask() operations only mask/unmask the
100  *    So, a global interrupt is enabled at the per-CPU level as soon
104  *  - For per-CPU interrupts
106  *    At ->map() time, a per-CPU interrupt is unmasked at the global
109  *    The ->mask() and ->unmask() operations mask/unmask the interrupt
110  *    at the per-CPU level.
112  *    So, a per-CPU interrupt is enabled at the global level as soon
114  *    at the per-CPU level.
134 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)  argument
170  * For CPU interrupts, mask/unmask the calling CPU's bit
212 	unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data));  in armada_370_xp_compose_msi_msg()  local
214 	msg->address_lo = lower_32_bits(msi_doorbell_addr);  in armada_370_xp_compose_msi_msg()
215 	msg->address_hi = upper_32_bits(msi_doorbell_addr);  in armada_370_xp_compose_msi_msg()
216 	msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START);  in armada_370_xp_compose_msi_msg()
222 	unsigned int cpu;  in armada_370_xp_msi_set_affinity()  local
225 		cpu = cpumask_any_and(mask, cpu_online_mask);  in armada_370_xp_msi_set_affinity()
227 		cpu = cpumask_first(mask);  in armada_370_xp_msi_set_affinity()
229 	if (cpu >= nr_cpu_ids)  in armada_370_xp_msi_set_affinity()
230 		return -EINVAL;  in armada_370_xp_msi_set_affinity()
232 	irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));  in armada_370_xp_msi_set_affinity()
254 		return -ENOSPC;  in armada_370_xp_msi_alloc()
259 				    domain->host_data, handle_simple_irq,  in armada_370_xp_msi_alloc()
272 	bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));  in armada_370_xp_msi_free()
285 	/* Enable MSI doorbell mask and combined cpu local interrupt */  in armada_370_xp_msi_reenable_percpu()
303 		return -ENOMEM;  in armada_370_xp_msi_init()
311 		return -ENOMEM;  in armada_370_xp_msi_init()
336 	if (!of_machine_is_compatible("marvell,armada-370-xp"))  in armada_xp_mpic_perf_init()
353 	reg &= ~BIT(d->hwirq);  in armada_370_xp_ipi_mask()
361 	reg |= BIT(d->hwirq);  in armada_370_xp_ipi_unmask()
369 	int cpu;  in armada_370_xp_ipi_send_mask()  local
371 	/* Convert our logical CPU mask into a physical one. */  in armada_370_xp_ipi_send_mask()
372 	for_each_cpu(cpu, mask)  in armada_370_xp_ipi_send_mask()
373 		map |= 1 << cpu_logical_map(cpu);  in armada_370_xp_ipi_send_mask()
382 	writel((map << 8) | d->hwirq, main_int_base +  in armada_370_xp_ipi_send_mask()
388 	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);  in armada_370_xp_ipi_ack()
408 				    d->host_data,  in armada_370_xp_ipi_alloc()
457 	base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END,  in armada_xp_ipi_init()
472 	int cpu;  in armada_xp_set_affinity()  local
475 	cpu = cpumask_any_and(mask_val, cpu_online_mask);  in armada_xp_set_affinity()
476 	mask = 1UL << cpu_logical_map(cpu);  in armada_xp_set_affinity()
484 	irq_data_update_effective_affinity(d, cpumask_of(cpu));  in armada_xp_set_affinity()
514 	/* Re-enable per-CPU interrupts that were enabled before suspend */  in armada_xp_mpic_reenable_percpu()
536 static int armada_xp_mpic_starting_cpu(unsigned int cpu)  in armada_xp_mpic_starting_cpu()  argument
544 static int mpic_cascaded_starting_cpu(unsigned int cpu)  in mpic_cascaded_starting_cpu()  argument
616 		irq = msinr - PCI_MSI_DOORBELL_START;  in armada_370_xp_handle_msi_irq()
639 		/* Check if the interrupt is not masked on current CPU.  in armada_370_xp_mpic_handle_cascade_irq()
640 		 * Test IRQ (0-1) and FIQ (8-9) mask bits.  in armada_370_xp_mpic_handle_cascade_irq()
709 	/* Re-enable interrupts */  in armada_370_xp_mpic_resume()
722 			/* Non per-CPU interrupts */  in armada_370_xp_mpic_resume()
728 			/* Per-CPU interrupts */  in armada_370_xp_mpic_resume()
733 			 * Re-enable on the current CPU,  in armada_370_xp_mpic_resume()
770 				   node->full_name));  in armada_370_xp_mpic_of_init()
773 				   node->full_name));  in armada_370_xp_mpic_of_init()
795 	/* Setup for the boot CPU */  in armada_370_xp_mpic_of_init()