Lines Matching +full:soc +full:- +full:ip

1 # SPDX-License-Identifier: GPL-2.0-only
118 	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
126 	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
213 	bool "J-Core integrated AIC" if COMPILE_TEST
217 	  Support for the J-Core integrated AIC.
228 	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
231 	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
236 	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
246 	bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
250 	  Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
286 	tristate "TS-4800 IRQ controller"
291 	  Support for the TS-4800 FPGA IRQ controller
308 	bool "Xilinx Interrupt Controller IP"
312 	  Support for the Xilinx Interrupt Controller IP core.
319 	  Support for a CROSSBAR ip that precedes the main interrupt controller.
321 	  a free irq and configures the IP. Thus the peripheral interrupts are
325 	tristate "Keystone 2 IRQ controller IP"
328 		Support for Texas Instruments Keystone 2 IRQ controller IP which
424          Support Meson SoC Family GPIO Interrupt Multiplexer
456 	  Say yes here to enable C-SKY SMP interrupt controller driver used
457 	  for C-SKY SMP system.
462 	bool "C-SKY APB Interrupt Controller"
465 	  Say yes here to enable C-SKY APB interrupt controller driver used
466 	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
494 	  CPU-to-CPU MSI controller. This requires a specially crafted DT
500 	bool "Loongson-1 Interrupt Controller"
506 	  Support for the Loongson-1 platform Interrupt Controller.
535 	  This enables support for the PRU-ICSS Local Interrupt Controller
536 	  present within a PRU-ICSS subsystem present on various TI SoCs.
538 	  different processors within the SoC.
541 	bool "RISC-V Local Interrupt Controller"
545 	   This enables support for the per-HART local interrupt controller
546 	   found in standard RISC-V systems.  The per-HART local interrupt
548 	   hardware interrupts. Without a per-HART local interrupt controller,
549 	   a RISC-V system will be unable to handle any interrupts.
554 	bool "SiFive Platform-Level Interrupt Controller"
560 	   potentially other) RISC-V systems.  The PLIC controls devices
587 	  Documentation/loongarch/irq-chip-model.rst.
615 	  Support for the Loongson-3 HyperTransport PIC Controller.
666 	  Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
693 	  Support for the Sunplus SP7021 Interrupt Controller IP core.
694 	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
695 	  chained controller, routing all interrupt source in P-Chip to
696 	  the primary controller on C-Chip.