210 	struct mtk_iommu_domain		*m4u_dom; /* Each bank has a domain */  member
414 	struct mtk_iommu_domain *dom = bank->m4u_dom;  in mtk_iommu_isr()
581 	struct mtk_iommu_domain	*m4u_dom;  in mtk_iommu_domain_finalise()  local
584 	m4u_dom = data->bank[0].m4u_dom;  in mtk_iommu_domain_finalise()
585 	if (m4u_dom) {  in mtk_iommu_domain_finalise()
586 		dom->iop = m4u_dom->iop;  in mtk_iommu_domain_finalise()
587 		dom->cfg = m4u_dom->cfg;  in mtk_iommu_domain_finalise()
588 		dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;  in mtk_iommu_domain_finalise()
679 	if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */  in mtk_iommu_attach_device()
691 		bank->m4u_dom = dom;  in mtk_iommu_attach_device()
1195 		bank->m4u_dom = NULL;  in mtk_iommu_probe()
1287 		if (!bank->m4u_dom)  in mtk_iommu_remove()
1323 	struct mtk_iommu_domain *m4u_dom;  in mtk_iommu_runtime_resume()  local
1347 		m4u_dom = data->bank[i].m4u_dom;  in mtk_iommu_runtime_resume()
1348 		if (!data->plat_data->banks_enable[i] || !m4u_dom)  in mtk_iommu_runtime_resume()
1354 		writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);  in mtk_iommu_runtime_resume()