Lines Matching +full:mt6795 +full:- +full:larb +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
11 #include <linux/dma-direct.h>
17 #include <linux/io-pgtable.h>
34 #include <dt-bindings/memory/mtk-memory-port.h>
144 ((((pdata)->flags) & (mask)) == (_x))
233 * In the sharing pgtable case, list data->list to the global list like m4ulist.
234 * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
256 return component_bind_all(dev, &data->larb_imu); in mtk_iommu_bind()
263 component_unbind_all(dev, &data->larb_imu); in mtk_iommu_unbind()
282 * |---A---|---B---|---C---|---D---|---E---|
283 * +--I/O--+------------Memory-------------+
289 * |---E---|---B---|---C---|---D---|
290 * +------------Memory-------------+
333 struct mtk_iommu_bank_data *bank = &data->bank[0]; in mtk_iommu_tlb_flush_all()
334 void __iomem *base = bank->base; in mtk_iommu_tlb_flush_all()
337 spin_lock_irqsave(&bank->tlb_lock, flags); in mtk_iommu_tlb_flush_all()
338 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_all()
341 spin_unlock_irqrestore(&bank->tlb_lock, flags); in mtk_iommu_tlb_flush_all()
347 struct list_head *head = bank->parent_data->hw_list; in mtk_iommu_tlb_flush_range_sync()
372 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); in mtk_iommu_tlb_flush_range_sync()
375 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_range_sync()
379 curbank = &data->bank[bank->id]; in mtk_iommu_tlb_flush_range_sync()
380 base = curbank->base; in mtk_iommu_tlb_flush_range_sync()
382 spin_lock_irqsave(&curbank->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
384 base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_range_sync()
387 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), in mtk_iommu_tlb_flush_range_sync()
397 spin_unlock_irqrestore(&curbank->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
400 dev_warn(data->dev, in mtk_iommu_tlb_flush_range_sync()
406 pm_runtime_put(data->dev); in mtk_iommu_tlb_flush_range_sync()
413 struct mtk_iommu_data *data = bank->parent_data; in mtk_iommu_isr()
414 struct mtk_iommu_domain *dom = bank->m4u_dom; in mtk_iommu_isr()
417 const struct mtk_iommu_plat_data *plat_data = data->plat_data; in mtk_iommu_isr()
418 void __iomem *base = bank->base; in mtk_iommu_isr()
454 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; in mtk_iommu_isr()
457 if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, in mtk_iommu_isr()
460 bank->parent_dev, in mtk_iommu_isr()
461 "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", in mtk_iommu_isr()
482 if (plat_data->banks_num == 1) in mtk_iommu_get_bank_id()
485 for (i = 0; i < fwspec->num_ids; i++) in mtk_iommu_get_bank_id()
486 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); in mtk_iommu_get_bank_id()
488 for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { in mtk_iommu_get_bank_id()
489 if (!plat_data->banks_enable[i]) in mtk_iommu_get_bank_id()
492 if (portmsk & plat_data->banks_portmsk[i]) { in mtk_iommu_get_bank_id()
503 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; in mtk_iommu_get_iova_region_id()
504 const struct bus_dma_region *dma_rgn = dev->dma_range_map; in mtk_iommu_get_iova_region_id()
505 int i, candidate = -1; in mtk_iommu_get_iova_region_id()
508 if (!dma_rgn || plat_data->iova_region_nr == 1) in mtk_iommu_get_iova_region_id()
511 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; in mtk_iommu_get_iova_region_id()
512 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { in mtk_iommu_get_iova_region_id()
514 if (dma_rgn->dma_start == rgn->iova_base && in mtk_iommu_get_iova_region_id()
515 dma_end == rgn->iova_base + rgn->size - 1) in mtk_iommu_get_iova_region_id()
518 if (dma_rgn->dma_start >= rgn->iova_base && in mtk_iommu_get_iova_region_id()
519 dma_end < rgn->iova_base + rgn->size) in mtk_iommu_get_iova_region_id()
526 &dma_rgn->dma_start, dma_rgn->size); in mtk_iommu_get_iova_region_id()
527 return -EINVAL; in mtk_iommu_get_iova_region_id()
540 for (i = 0; i < fwspec->num_ids; ++i) { in mtk_iommu_config()
541 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); in mtk_iommu_config()
542 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); in mtk_iommu_config()
544 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_config()
545 larb_mmu = &data->larb_imu[larbid]; in mtk_iommu_config()
547 region = data->plat_data->iova_region + regionid; in mtk_iommu_config()
548 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); in mtk_iommu_config()
550 dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", in mtk_iommu_config()
551 enable ? "enable" : "disable", dev_name(larb_mmu->dev), in mtk_iommu_config()
552 portid, regionid, larb_mmu->bank[portid]); in mtk_iommu_config()
555 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
557 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
558 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { in mtk_iommu_config()
565 ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, in mtk_iommu_config()
570 dev_name(data->dev), peri_mmuen_msk, ret); in mtk_iommu_config()
584 m4u_dom = data->bank[0].m4u_dom; in mtk_iommu_domain_finalise()
586 dom->iop = m4u_dom->iop; in mtk_iommu_domain_finalise()
587 dom->cfg = m4u_dom->cfg; in mtk_iommu_domain_finalise()
588 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
592 dom->cfg = (struct io_pgtable_cfg) { in mtk_iommu_domain_finalise()
597 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, in mtk_iommu_domain_finalise()
598 .iommu_dev = data->dev, in mtk_iommu_domain_finalise()
601 if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) in mtk_iommu_domain_finalise()
602 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; in mtk_iommu_domain_finalise()
604 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) in mtk_iommu_domain_finalise()
605 dom->cfg.oas = data->enable_4GB ? 33 : 32; in mtk_iommu_domain_finalise()
607 dom->cfg.oas = 35; in mtk_iommu_domain_finalise()
609 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); in mtk_iommu_domain_finalise()
610 if (!dom->iop) { in mtk_iommu_domain_finalise()
611 dev_err(data->dev, "Failed to alloc io pgtable\n"); in mtk_iommu_domain_finalise()
612 return -EINVAL; in mtk_iommu_domain_finalise()
616 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
620 region = data->plat_data->iova_region + region_id; in mtk_iommu_domain_finalise()
621 dom->domain.geometry.aperture_start = region->iova_base; in mtk_iommu_domain_finalise()
622 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; in mtk_iommu_domain_finalise()
623 dom->domain.geometry.force_aperture = true; in mtk_iommu_domain_finalise()
637 mutex_init(&dom->mutex); in mtk_iommu_domain_alloc()
639 return &dom->domain; in mtk_iommu_domain_alloc()
652 struct list_head *hw_list = data->hw_list; in mtk_iommu_attach_device()
653 struct device *m4udev = data->dev; in mtk_iommu_attach_device()
658 region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); in mtk_iommu_attach_device()
662 bankid = mtk_iommu_get_bank_id(dev, data->plat_data); in mtk_iommu_attach_device()
663 mutex_lock(&dom->mutex); in mtk_iommu_attach_device()
664 if (!dom->bank) { in mtk_iommu_attach_device()
670 mutex_unlock(&dom->mutex); in mtk_iommu_attach_device()
671 return -ENODEV; in mtk_iommu_attach_device()
673 dom->bank = &data->bank[bankid]; in mtk_iommu_attach_device()
675 mutex_unlock(&dom->mutex); in mtk_iommu_attach_device()
677 mutex_lock(&data->mutex); in mtk_iommu_attach_device()
678 bank = &data->bank[bankid]; in mtk_iommu_attach_device()
679 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ in mtk_iommu_attach_device()
691 bank->m4u_dom = dom; in mtk_iommu_attach_device()
692 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
696 mutex_unlock(&data->mutex); in mtk_iommu_attach_device()
701 mutex_unlock(&data->mutex); in mtk_iommu_attach_device()
719 if (dom->bank->parent_data->enable_4GB) in mtk_iommu_map()
723 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); in mtk_iommu_map()
733 return dom->iop->unmap(dom->iop, iova, size, gather); in mtk_iommu_unmap()
740 mtk_iommu_tlb_flush_all(dom->bank->parent_data); in mtk_iommu_flush_iotlb_all()
747 size_t length = gather->end - gather->start + 1; in mtk_iommu_iotlb_sync()
749 mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); in mtk_iommu_iotlb_sync()
757 mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); in mtk_iommu_sync_map()
766 pa = dom->iop->iova_to_phys(dom->iop, iova); in mtk_iommu_iova_to_phys()
768 dom->bank->parent_data->enable_4GB && in mtk_iommu_iova_to_phys()
783 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_probe_device()
784 return ERR_PTR(-ENODEV); /* Not a iommu client device */ in mtk_iommu_probe_device()
788 if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) in mtk_iommu_probe_device()
789 return &data->iommu; in mtk_iommu_probe_device()
792 * Link the consumer device with the smi-larb device(supplier). in mtk_iommu_probe_device()
793 * The device that connects with each a larb is a independent HW. in mtk_iommu_probe_device()
796 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); in mtk_iommu_probe_device()
798 return ERR_PTR(-EINVAL); in mtk_iommu_probe_device()
800 for (i = 1; i < fwspec->num_ids; i++) { in mtk_iommu_probe_device()
801 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); in mtk_iommu_probe_device()
803 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", in mtk_iommu_probe_device()
805 return ERR_PTR(-EINVAL); in mtk_iommu_probe_device()
808 larbdev = data->larb_imu[larbid].dev; in mtk_iommu_probe_device()
810 return ERR_PTR(-EINVAL); in mtk_iommu_probe_device()
816 return &data->iommu; in mtk_iommu_probe_device()
827 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_release_device()
828 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); in mtk_iommu_release_device()
829 larbdev = data->larb_imu[larbid].dev; in mtk_iommu_release_device()
852 struct list_head *hw_list = c_data->hw_list; in mtk_iommu_device_group()
858 return ERR_PTR(-ENODEV); in mtk_iommu_device_group()
860 groupid = mtk_iommu_get_group_id(dev, data->plat_data); in mtk_iommu_device_group()
864 mutex_lock(&data->mutex); in mtk_iommu_device_group()
865 group = data->m4u_group[groupid]; in mtk_iommu_device_group()
869 data->m4u_group[groupid] = group; in mtk_iommu_device_group()
873 mutex_unlock(&data->mutex); in mtk_iommu_device_group()
881 if (args->args_count != 1) { in mtk_iommu_of_xlate()
882 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", in mtk_iommu_of_xlate()
883 args->args_count); in mtk_iommu_of_xlate()
884 return -EINVAL; in mtk_iommu_of_xlate()
889 m4updev = of_find_device_by_node(args->np); in mtk_iommu_of_xlate()
891 return -EINVAL; in mtk_iommu_of_xlate()
896 return iommu_fwspec_add_ids(dev, args->args, 1); in mtk_iommu_of_xlate()
903 unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; in mtk_iommu_get_resv_regions()
910 curdom = data->plat_data->iova_region + regionid; in mtk_iommu_get_resv_regions()
911 for (i = 0; i < data->plat_data->iova_region_nr; i++) { in mtk_iommu_get_resv_regions()
912 resv = data->plat_data->iova_region + i; in mtk_iommu_get_resv_regions()
915 if (resv->iova_base <= curdom->iova_base || in mtk_iommu_get_resv_regions()
916 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) in mtk_iommu_get_resv_regions()
919 region = iommu_alloc_resv_region(resv->iova_base, resv->size, in mtk_iommu_get_resv_regions()
925 list_add_tail(®ion->list, head); in mtk_iommu_get_resv_regions()
953 const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; in mtk_iommu_hw_init()
954 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; in mtk_iommu_hw_init()
958 * Global control settings are in bank0. May re-init these global registers in mtk_iommu_hw_init()
961 if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { in mtk_iommu_hw_init()
965 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
968 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
970 if (data->enable_4GB && in mtk_iommu_hw_init()
971 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { in mtk_iommu_hw_init()
977 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); in mtk_iommu_hw_init()
979 if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) in mtk_iommu_hw_init()
980 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
982 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
984 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { in mtk_iommu_hw_init()
986 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
988 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
991 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { in mtk_iommu_hw_init()
995 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
996 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) in mtk_iommu_hw_init()
998 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) in mtk_iommu_hw_init()
1001 writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
1010 writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); in mtk_iommu_hw_init()
1019 writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_hw_init()
1021 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) in mtk_iommu_hw_init()
1022 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); in mtk_iommu_hw_init()
1024 regval = lower_32_bits(data->protect_base) | in mtk_iommu_hw_init()
1025 upper_32_bits(data->protect_base); in mtk_iommu_hw_init()
1026 writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); in mtk_iommu_hw_init()
1028 if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, in mtk_iommu_hw_init()
1029 dev_name(bankx->parent_dev), (void *)bankx)) { in mtk_iommu_hw_init()
1030 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
1031 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); in mtk_iommu_hw_init()
1032 return -ENODEV; in mtk_iommu_hw_init()
1051 larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); in mtk_iommu_mm_dts_parse()
1058 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); in mtk_iommu_mm_dts_parse()
1060 return -EINVAL; in mtk_iommu_mm_dts_parse()
1067 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); in mtk_iommu_mm_dts_parse()
1074 return -ENODEV; in mtk_iommu_mm_dts_parse()
1076 if (!plarbdev->dev.driver) { in mtk_iommu_mm_dts_parse()
1078 return -EPROBE_DEFER; in mtk_iommu_mm_dts_parse()
1080 data->larb_imu[id].dev = &plarbdev->dev; in mtk_iommu_mm_dts_parse()
1086 /* Get smi-(sub)-common dev from the last larb. */ in mtk_iommu_mm_dts_parse()
1089 return -EINVAL; in mtk_iommu_mm_dts_parse()
1092 * It may have two level smi-common. the node is smi-sub-common if it in mtk_iommu_mm_dts_parse()
1093 * has a new mediatek,smi property. otherwise it is smi-commmon. in mtk_iommu_mm_dts_parse()
1103 data->smicomm_dev = &plarbdev->dev; in mtk_iommu_mm_dts_parse()
1105 link = device_link_add(data->smicomm_dev, dev, in mtk_iommu_mm_dts_parse()
1108 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); in mtk_iommu_mm_dts_parse()
1109 return -EINVAL; in mtk_iommu_mm_dts_parse()
1117 struct device *dev = &pdev->dev; in mtk_iommu_probe()
1131 return -ENOMEM; in mtk_iommu_probe()
1132 data->dev = dev; in mtk_iommu_probe()
1133 data->plat_data = of_device_get_match_data(dev); in mtk_iommu_probe()
1138 return -ENOMEM; in mtk_iommu_probe()
1139 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); in mtk_iommu_probe()
1141 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { in mtk_iommu_probe()
1142 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); in mtk_iommu_probe()
1152 switch (data->plat_data->m4u_plat) { in mtk_iommu_probe()
1154 p = "mediatek,mt2712-infracfg"; in mtk_iommu_probe()
1157 p = "mediatek,mt8173-infracfg"; in mtk_iommu_probe()
1171 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); in mtk_iommu_probe()
1174 banks_num = data->plat_data->banks_num; in mtk_iommu_probe()
1178 return -EINVAL; in mtk_iommu_probe()
1183 ioaddr = res->start; in mtk_iommu_probe()
1185 data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); in mtk_iommu_probe()
1186 if (!data->bank) in mtk_iommu_probe()
1187 return -ENOMEM; in mtk_iommu_probe()
1190 if (!data->plat_data->banks_enable[i]) in mtk_iommu_probe()
1192 bank = &data->bank[i]; in mtk_iommu_probe()
1193 bank->id = i; in mtk_iommu_probe()
1194 bank->base = base + i * MTK_IOMMU_BANK_SZ; in mtk_iommu_probe()
1195 bank->m4u_dom = NULL; in mtk_iommu_probe()
1197 bank->irq = platform_get_irq(pdev, i); in mtk_iommu_probe()
1198 if (bank->irq < 0) in mtk_iommu_probe()
1199 return bank->irq; in mtk_iommu_probe()
1200 bank->parent_dev = dev; in mtk_iommu_probe()
1201 bank->parent_data = data; in mtk_iommu_probe()
1202 spin_lock_init(&bank->tlb_lock); in mtk_iommu_probe()
1205 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { in mtk_iommu_probe()
1206 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
1207 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
1208 return PTR_ERR(data->bclk); in mtk_iommu_probe()
1213 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_probe()
1219 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { in mtk_iommu_probe()
1220 p = data->plat_data->pericfg_comp_str; in mtk_iommu_probe()
1221 data->pericfg = syscon_regmap_lookup_by_compatible(p); in mtk_iommu_probe()
1222 if (IS_ERR(data->pericfg)) { in mtk_iommu_probe()
1223 ret = PTR_ERR(data->pericfg); in mtk_iommu_probe()
1229 mutex_init(&data->mutex); in mtk_iommu_probe()
1231 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, in mtk_iommu_probe()
1232 "mtk-iommu.%pa", &ioaddr); in mtk_iommu_probe()
1236 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); in mtk_iommu_probe()
1240 if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { in mtk_iommu_probe()
1241 list_add_tail(&data->list, data->plat_data->hw_list); in mtk_iommu_probe()
1242 data->hw_list = data->plat_data->hw_list; in mtk_iommu_probe()
1244 INIT_LIST_HEAD(&data->hw_list_head); in mtk_iommu_probe()
1245 list_add_tail(&data->list, &data->hw_list_head); in mtk_iommu_probe()
1246 data->hw_list = &data->hw_list_head; in mtk_iommu_probe()
1249 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_probe()
1257 list_del(&data->list); in mtk_iommu_probe()
1258 iommu_device_unregister(&data->iommu); in mtk_iommu_probe()
1260 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_probe()
1262 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) in mtk_iommu_probe()
1263 device_link_remove(data->smicomm_dev, dev); in mtk_iommu_probe()
1275 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_remove()
1276 iommu_device_unregister(&data->iommu); in mtk_iommu_remove()
1278 list_del(&data->list); in mtk_iommu_remove()
1280 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { in mtk_iommu_remove()
1281 device_link_remove(data->smicomm_dev, &pdev->dev); in mtk_iommu_remove()
1282 component_master_del(&pdev->dev, &mtk_iommu_com_ops); in mtk_iommu_remove()
1284 pm_runtime_disable(&pdev->dev); in mtk_iommu_remove()
1285 for (i = 0; i < data->plat_data->banks_num; i++) { in mtk_iommu_remove()
1286 bank = &data->bank[i]; in mtk_iommu_remove()
1287 if (!bank->m4u_dom) in mtk_iommu_remove()
1289 devm_free_irq(&pdev->dev, bank->irq, bank); in mtk_iommu_remove()
1297 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_suspend()
1301 base = data->bank[i].base; in mtk_iommu_runtime_suspend()
1302 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_suspend()
1303 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_suspend()
1304 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_suspend()
1305 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_suspend()
1306 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_suspend()
1308 if (!data->plat_data->banks_enable[i]) in mtk_iommu_runtime_suspend()
1310 base = data->bank[i].base; in mtk_iommu_runtime_suspend()
1311 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_suspend()
1312 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_suspend()
1313 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_suspend()
1314 } while (++i < data->plat_data->banks_num); in mtk_iommu_runtime_suspend()
1315 clk_disable_unprepare(data->bclk); in mtk_iommu_runtime_suspend()
1322 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_resume()
1327 ret = clk_prepare_enable(data->bclk); in mtk_iommu_runtime_resume()
1329 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); in mtk_iommu_runtime_resume()
1337 if (!reg->wr_len_ctrl) in mtk_iommu_runtime_resume()
1340 base = data->bank[i].base; in mtk_iommu_runtime_resume()
1341 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_resume()
1342 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_resume()
1343 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_resume()
1344 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_resume()
1345 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_resume()
1347 m4u_dom = data->bank[i].m4u_dom; in mtk_iommu_runtime_resume()
1348 if (!data->plat_data->banks_enable[i] || !m4u_dom) in mtk_iommu_runtime_resume()
1350 base = data->bank[i].base; in mtk_iommu_runtime_resume()
1351 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_resume()
1352 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_resume()
1353 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_resume()
1354 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
1355 } while (++i < data->plat_data->banks_num); in mtk_iommu_runtime_resume()
1476 .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1520 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1521 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1522 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
1523 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1524 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1525 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1526 { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
1527 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1528 { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1529 { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
1530 { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
1538 .name = "mtk-iommu",